Top Design Engineer Jobs in Bangalore

Lead SoC front-end integration and assembly for Tegra chips. Ensure RTL quality, drive chip execution across milestones, develop system-level methodologies/tools, and collaborate with architecture, physical design, CAD, package, DFT and verification teams to improve SOC implementation efficiency.

Design, implement, validate, and debug DFT solutions (TAP/JTAG, IJTAG, BSCAN, MBIST, ATPG, scan compression) across IP and SoC. Drive test access, pattern generation, coverage optimization, memory test validation, silicon debug, RTL and gate-level validation, and cross-team DFT integration and signoff.

Design and architect high-performance blocks for networking ASICs. Perform micro-architecture and Verilog RTL logic design to maximize throughput and minimize power. Collaborate with verification and physical design teams on testplans, debug failures, timing constraints, and timing fixes for high-speed interfaces and memory subsystems.

The role involves IC layout design for high-performance memory circuits, leading layout architecture, verification, and mentoring junior engineers while optimizing design methodologies.

The Lead Design Engineer will perform design verification of ASICs, create test plans, develop functional coverage, and involve in post-silicon validation in a collaborative environment.

Seeking a Sr Principal Design Engineer with 12-14 years in VLSI, expertise in Verilog, HVL, UVM/OVM methodologies, and scripting skills.

The Principal Design Engineer will oversee semiconductor IP development, ensuring quality management, continuous process improvement, and maintaining design quality certifications.

Looking for a Sr Principal Design Engineer with 12-14 years of experience in VLSI, strong skills in Verilog and various methodologies, and expertise in test-bench development and project management.

The Lead Physical Design Engineer will manage and execute physical design tasks for high-performance semiconductor ICs, ensuring design integration and resolving issues related to power efficiency, timing, and area.

Define and lead system-level modeling and virtual prototyping for ADI SoCs; create high-fidelity SystemC/TLM virtual platforms; develop AI tools and automation for modeling; troubleshoot pre-silicon system issues; and collaborate with customers and cross-functional teams to enable early software development prior to silicon tape-out.

Design and calculate electrical and mechanical parameters for capacitor units and banks (HVDC/series). Create order drawings in AutoCAD, perform design calculations, prepare BOMs and upload to SAP/Digital Passport, support costing, manufacturing, testing, type-test coordination, and material planning for long-lead items. Provide design-related support to service teams and uphold safety and integrity values.

Execute end-to-end physical design for custom IP and SoC from RTL to GDS: synthesis, floorplanning, place-and-route, CTS, STA, signal integrity, power optimization, verification analysis, and methodology automation.

Lead physical verification and power-integrity signoff for block and full-chip mixed-signal designs. Perform DRC/LVS/PEX/PERC/ERC, antenna, density/DFM checks, and EM/IR drop analysis. Develop automation and scripts (Python, Tcl, Shell, SKILL), drive tapeout readiness, collaborate with layout/circuit/CAD/foundry teams, and mentor junior engineers.

Lead architecture and implementation of digital subsystems for Automotive Ethernet PHYs. Define micro-architecture, develop RTL (Verilog/SystemVerilog), drive digital front-end flows (lint, CDC/RDC, synthesis, STA), collaborate with mixed-signal and firmware teams, perform system partitioning, support bring-up/compliance testing, and ensure ISO 26262 and AEC-Q100 functional-safety compliance.

Design and execute advanced semiconductor package layouts (2.5D/3D, SiP, FCBGA, chiplets). Maintain CAD databases, generate manufacturing outputs, ensure DFM/DFA and foundry/OSAT rule compliance, support SI/PI/thermal/reliability co‑design, and manage ECO/version control through project lifecycle.

Lead full-chip physical design for high-performance processor SoCs across advanced nodes. Manage RTL-to-GDS implementation, timing, power, DFT, and physical verification; mentor engineers, drive automation and tooling, engage global stakeholders to deliver tape-outs.

Lead full-chip physical design for advanced-node processor/ASIC products: manage RTL-to-GDS flows, multi-million-gate hierarchical partitioning, clock tree and IO planning, ensure EM/IR, timing, DFM, and PV sign-offs, mentor engineers, and drive cross-functional design execution.

Lead physical design engineer driving RTL-to-GDSII implementation and methodology development for high-performance processor ASICs. Responsible for synthesis, floorplanning, place-and-route, clock tree synthesis, timing closure, STA, power/signal integrity, automation flows, EDA tool evaluation, cross-functional collaboration, and mentoring engineers.

Lead and perform custom analog/layout design for high-speed IPs (SerDes, DDR, PCIe, HBM, chiplets). Collaborate with circuit, digital, packaging, and foundry teams. Execute physical verifications (DRC, LVS, electrical checks, ageing/reliability). Mentor or lead engineers, adapt to new nodes/technologies, and apply scripting/automation to improve flows.

Design and develop microarchitecture and RTL for SoC subsystems, lead SoC integration for ARM-based automotive MCUs, collaborate with IP, systems, DV/DFT/emulation teams, participate in debug and design reviews, and ensure timing, power, and testability requirements are met.

Lead end-to-end hardware design for high-speed, high-density Ethernet switches: specify components, capture schematics, collaborate on PCB layout and signal/power integrity simulations, drive lab bring-up and production ramp, work with CMs, and mentor junior engineers.

Design, model, and produce conveyor, ASRS, and material handling equipment using SolidWorks and AutoCAD; perform mechanical calculations, tolerance analysis, component selection, FEA, and DFMEA; collaborate with cross-functional teams, support prototyping, produce manufacturing drawings, BOMs, technical documentation, and ensure compliance with standards.

Design, modify, and troubleshoot complex electrical assemblies, schematics, and controllers. Perform engineering analysis and test reports, lead projects and suppliers, resolve technical issues, and produce product specifications and documentation to support semiconductor/display equipment.

Lead complex digital design projects, define architectures, mentor engineers, and collaborate across functions to drive innovation in digital design.

The Staff Physical Design Engineer oversees end-to-end physical design for complex SoCs, leads a team, and drives methodology improvements while mentoring junior engineers and communicating across departments.