Top Design Engineer Jobs in Bangalore

Reposted 3 Days AgoSaved
In-Office
2 Locations
Senior level
Senior level
Automotive • Cloud • Energy
The Staff Digital Design Engineer will lead digital design architecture, RTL implementation, and collaborate with multidisciplinary teams to develop Power Management ICs, ensuring high quality and performance.
Top Skills: AsicDigital RtlPerlPythonSystem VerilogTclVerilogXML
Reposted 3 Days AgoSaved
In-Office
2 Locations
10-10 Annually
Senior level
10-10 Annually
Senior level
Automotive • Cloud • Energy
Lead digital design architecture and RTL implementation for power management ICs. Collaborate across teams, support validation, and improve design processes.
Top Skills: AsicCdcP&RPerlPythonRtlSystem VerilogTclUpfVerilogXML
Reposted 3 Days AgoSaved
In-Office
2 Locations
Senior level
Senior level
Automotive • Cloud • Energy
The role involves leading digital design architecture, RTL implementation, trade-off analysis, and collaborating with global teams on ASIC development projects. Responsibilities include enhancing design methodologies and managing multiple projects within the team.
Top Skills: Asic DesignPerlPythonRtl DesignSystem VerilogTclVerilogXML
Reposted 3 Days AgoSaved
In-Office
2 Locations
Senior level
Senior level
Automotive • Cloud • Energy
Design and develop analog IP blocks for power management products, collaborating with teams on verification and execution while guiding layout processes.
Top Skills: Cadence SpectreCmos Analog DesignGan)Led DriversMatlabPower Management DesignSimplisWbg Drivers (Sic
Reposted 3 Days AgoSaved
In-Office
2 Locations
150K-220K Annually
Senior level
150K-220K Annually
Senior level
Automotive • Cloud • Energy
The MTS Analog Design Engineer will lead and mentor a team in developing power management products, ensuring technical objectives are met, and collaborating with various teams to facilitate product release and customer support.
Top Skills: Analog Ic DesignCadence SpectreLed DriversMatlabMos/Igbt DriversPower ManagementSic DriversSmart Switches
Reposted 3 Days AgoSaved
In-Office
2 Locations
Senior level
Senior level
Automotive • Cloud • Energy
Lead the design and verification of a digital sub-system within the Treo platform. Collaborate with teams to ensure requirements are met and IP meets ASIL standards. Perform RTL coding and scripting, drive innovation, and provide documentation.
Top Skills: AhbApbAxiCdcDesign CompilerDmaI2CLintPerlPythonRdcSpiSystem VerilogVerilog
Reposted 3 Days AgoSaved
In-Office
2 Locations
60K-120K Annually
Senior level
60K-120K Annually
Senior level
Automotive • Cloud • Energy
Design and develop analog IP blocks for power management, oversee block-level design and simulation, and work with various engineering teams for implementation and validation.
Top Skills: Analog DesignCadence SpectreCmosDc-Dc PmicGan)Led DriversMatlabWbg Drivers (Sic
Reposted 3 Days AgoSaved
In-Office
2 Locations
6-6 Annually
Senior level
6-6 Annually
Senior level
Automotive • Cloud • Energy
The role involves defining and implementing digital blocks, collaborating with teams, scripting for automation, and contributing to debugging and communication efforts.
Top Skills: PerlPythonRtlTcl
Reposted 3 Days AgoSaved
In-Office
2 Locations
Expert/Leader
Expert/Leader
Automotive • Internet of Things • Mobile • Semiconductor • Industrial
Lead and mentor engineers in physical design methodology, perform power analysis, and ensure the timely delivery of semiconductor designs.
Top Skills: Ansys RedhawkCadence InnovusIcc2PerlPowersiPythonSynopsys Fusion CompilerTcl
Reposted 3 Days AgoSaved
In-Office
2 Locations
Senior level
Senior level
Artificial Intelligence • Computer Vision • Hardware • Robotics • Metaverse
Lead block and chip level physical design activities for GPUs and ASICs, ensuring design challenges are addressed and improving RTL2GDS flow. Collaborate with design teams and troubleshoot design issues.
Top Skills: GpuIcc2InnovusPerlPrimetimeRtl2GdsiiSocTclTempus
Reposted 3 Days AgoSaved
In-Office
Bangalore, Bengaluru Urban, Karnataka, IND
Senior level
Senior level
Energy
The Aeroderivative Mechanical Design Engineer will lead design activities for gas turbine systems, manage mechanical durability tasks, perform FEM analysis, and optimize designs while collaborating with various engineering teams.
Top Skills: Ansys ClassicAnsys Topology OptimizationAnsys WorkbenchNx (Unigraphics)Teamcenter
4 Days AgoSaved
In-Office
Bangalore, Bengaluru Urban, Karnataka, IND
Mid level
Mid level
Artificial Intelligence • Cloud • Information Technology • Software
The Physical Design Engineer will design custom IP and SoC from RTL to GDS, focusing on synthesis, layout, and timing analysis, and will optimize for performance and reliability.
Top Skills: Clock Tree SynthesisEda ToolsFloor PlanningGdsPlace And RoutePower DistributionPower IntegrityRtlStatic Timing AnalysisSynthesis
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4 Days AgoSaved
In-Office
Bangalore, Bengaluru, Karnataka, IND
Junior
Junior
Hardware • Information Technology • Energy • Design • Utilities • Industrial • Renewable Energy
The R&D Design Engineer will design and analyze products, work with teams to meet customer requirements, and support prototyping and testing while applying mechanical engineering expertise.
Top Skills: 3D CadComputational Fluid DynamicsFinite Element AnalysisSolidworks
4 Days AgoSaved
In-Office
Bangalore, Bengaluru Urban, Karnataka, IND
Senior level
Senior level
Artificial Intelligence • Hardware • Automation • Manufacturing
The Staff Digital Design Engineer leads digital design projects, influences product direction, mentors engineers, and guides best practices across multiple technical domains.
Top Skills: Computer EngineeringDigital DesignElectrical EngineeringSystem Architecture
4 Days AgoSaved
In-Office
Bengaluru, Bengaluru Urban, Karnataka, IND
Mid level
Mid level
Energy • Manufacturing • Solar • Renewable Energy
Design and develop mechanical products while adhering to engineering principles. Engage in the analysis and evaluation of projects, support junior team members, and build customer relationships.
Top Skills: Mechanical Engineering
4 Days AgoSaved
In-Office
Bangalore, Bengaluru Urban, Karnataka, IND
Senior level
Senior level
Artificial Intelligence • Cloud • Hardware • Software • Semiconductor
Design high-speed D2D and SERDES products, develop analog/mixed signal IC circuit blocks, collaborate on circuit design and verification.
Top Skills: Cad ToolsCadence ToolsCmosIc DesignSerdes
Reposted 4 Days AgoSaved
In-Office
Bengaluru, Bengaluru Urban, Karnataka, IND
Senior level
Senior level
Artificial Intelligence • Cloud • Information Technology • Consulting
The Senior Hardware Design Engineer will lead complex hardware designs, mentor engineers, and make key technical decisions in networking systems.
Top Skills: Amd X86ArmBiosBootloadersCadence Pcb Design ToolsDdrElectrical EngineeringElectronicsEthernet PhyHigh-Speed Board-Level Hardware DesignsIntel X86I²CLinuxMdiPciePoeSgmiiSpiUartUsbXaui
Reposted 4 Days AgoSaved
In-Office
Bengaluru, Bengaluru Urban, Karnataka, IND
16-16 Annually
Expert/Leader
16-16 Annually
Expert/Leader
Artificial Intelligence • Cloud • Information Technology • Consulting
Lead hardware design for advanced networking platforms, define architecture, guide design standards, and mentor engineers in system-level solutions.
Top Skills: Cadence Pcb ToolsDdr4Ethernet PhysHigh-Bandwidth OscilloscopesHigh-Speed Digital DesignJtagPciePower Architecture
Reposted 4 Days AgoSaved
In-Office
Bangalore, Bengaluru Urban, Karnataka, IND
Senior level
Senior level
Artificial Intelligence • Automotive • Semiconductor
The Digital IC Design Staff Engineer will architect and deliver high-speed mixed signal IP, focusing on RTL design and development while mentoring junior engineers.
Top Skills: DdrEthernetPcieSpyglassSystem VerilogUcieUsbVerilogVhdl
Reposted 10 Days AgoSaved
In-Office
Bangalore, Bengaluru Urban, Karnataka, IND
Senior level
Senior level
Cloud • Information Technology • Internet of Things • Machine Learning • Software • Cybersecurity • Infrastructure as a Service (IaaS)
As a Senior Engineer in ASIC Design, you'll develop and document ASIC IP blocks, optimize design methodologies, and collaborate on cutting-edge 5G and 6G technologies.
Top Skills: AmbaAsic DesignAxiCadenceChiJenkinsJIRAPythonSimscopeSpyglassSynopsysSystemverilogTcl
Reposted 11 Days AgoSaved
In-Office
Bengaluru, Bengaluru Urban, Karnataka, IND
Senior level
Senior level
Artificial Intelligence • Hardware • Information Technology • Machine Learning
The role involves ownership and design of analog sub-blocks in high-speed PHYs, mentoring junior engineers, and collaborating on complex circuit designs.
Top Skills: Cadence AdeCalibreCmosMatlabPythonSpectreVerilog-A
Reposted 5 Days AgoSaved
In-Office
Bengaluru, Bengaluru Urban, Karnataka, IND
Senior level
Senior level
Artificial Intelligence • Computer Vision • Hardware • Robotics • Metaverse
Design complex ASIC memory subsystem components in collaboration with architects and verification teams, focusing on micro-architecture, RTL development, and post-silicon verification.
Top Skills: DebussyGdbPerlPythonRtlShellVcsVerilog
Reposted 5 Days AgoSaved
In-Office
Bangalore, Bengaluru Urban, Karnataka, IND
Senior level
Senior level
Artificial Intelligence • Cloud • Information Technology • Software
The Senior SoC Logic Design Engineer will design and develop SoC solutions, oversee RTL coding and simulation, and ensure integration and quality of designs for various applications.
Top Skills: AsicIp IntegrationRtlSoc
Reposted 5 Days AgoSaved
In-Office
Bangalore, Bengaluru Urban, Karnataka, IND
Senior level
Senior level
Artificial Intelligence • Cloud • Hardware • Software • Semiconductor
The role involves leading VLSI design engineering, overseeing project schedules, and developing complex test benches and verification methodologies.
Top Skills: AssertionsConstraint RandomizationErmFormal VerificationGlsHvlOvmPerlRtlSpecman ESystemverilogTclUvmVerilogVlsi
Reposted 5 Days AgoSaved
In-Office
2 Locations
Senior level
Senior level
Artificial Intelligence • Cloud • Hardware • Software • Semiconductor
Lead DFT ownership across projects: define test architecture, implement RTL DFT changes, perform scan insertion/LEC/CLP checks, develop test-mode timing constraints, run ATPG and timing simulations, implement/verify boundary-scan, ACJTAG, IEEE1500 and IEEE1687 (iJTAG) ICL/PDL, support post-silicon bring-up, and interact with customers and pre-sales.
Top Skills: AcjtagAtpgBoundary ScanClp ChecksDftHigh-Speed DesignIclIeee 1500Ieee 1687IjtagLec ChecksLow Power DesignPdlPost-Silicon Bring-UpRtlScan InsertionTiming ConstraintsTiming Simulation
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