Top Design Engineer Jobs in Bangalore

The Senior Design Engineer will build Android UI components, collaborate on design systems, and maintain stable user experiences while supporting product teams.

As a Design Engineer specializing in Pumps, you will coordinate manufacturing processes, improve methods, analyze quality and costs, and provide production support.

The Principal Design Engineer will be responsible for the design verification of IPs, including developing UVM testbenches and formal verification.

The role involves IP integration, verification, and release, focusing on RTL integration and debugging, with significant required experience in design processes.

The Principal DFT Design Engineer will mentor junior engineers, lead DFT projects, use EDA tools, and drive innovation in testing methodologies.

The Design Engineer II will perform post-silicon physical layer electrical validation, manage teams, and lead validation efforts for high-speed SERDES protocols.

Develop firmware for DDR/LPDDR/GDDR/HBM PHY, collaborate on algorithms, and support debugging of firmware simulations and hardware.

The Sr Principal RTL Design Engineer will design ASICs, utilizing Verilog for RTL design and managing interface protocols, while ensuring proper checks and simulations.

The Principal Design Engineer will oversee semiconductor IP development, ensuring quality management, continuous process improvement, and maintaining design quality certifications.

The role involves RTL design and support for DDR Memory Controller IP, including design updates, customer support, and adherence to design guidelines.

This role involves design verification for IP development, requiring expertise in UVM testbench development and formal verification processes for various interface designs.

The Principal Design Engineer will oversee integration and verification of DDR IP subsystems, support silicon bring-up, and resolve complex integration issues while working with global teams.

Design and integrate interfaces within FPGA components, develop digital designs in Verilog, and support validation processes while collaborating with cross-functional teams.

The Principal Design Engineer will manage design verification for interconnect IP, craft and execute verification plans, and collaborate with cross-functional teams.

Develops logic design and RTL coding for FPGAs, ensuring correct integration and performance within SoC architectures, including verification and testing.

Design and verify IO and mixed signal circuits, collaborate with layout engineers, develop functional models, and support silicon validation and customer requirements.

The Senior Physical Design Engineer will implement physical designs for semiconductor devices, optimizing layout, power, and performance from RTL to GDSII while collaborating with cross-functional teams.

Responsible for BOOT and power management architecture in next-gen chips, micro-architecture development, and working with cross-functional teams for verification and validation.

The RF Design Engineer will focus on designing, simulating, and verifying RF circuit blocks, collaborating with internal teams to enhance designs.

The Sr Principal Design Engineer will oversee the physical design process of complex Memory IPs, mentor junior engineers, and ensure design compliance with specifications.

The Memory Design Engineer will design, simulate, and verify custom memory blocks such as SRAM and ROM, collaborate with various teams, and support silicon bring-up.

The SoC Silicon Design Engineer will develop logic design, write RTL code, integrate IP blocks, optimize designs for power and timing, and ensure design verification and security compliance.

As a Senior SOC Design Engineer, you will drive SOC assembly, manage chip design functions, ensure design quality, and develop efficient methodologies for SOCs.

The Senior 4D Design Engineer will develop 4D models of construction sequences, collaborate with professionals, troubleshoot issues, and present visualizations to stakeholders.

The Analog Digital Mask Design Engineer will execute high-performance IC layout for CMOS integrated circuits, optimize designs, and verify layouts while following industry standards.