As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.
At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.
Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.
Are you ready?
To learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.
Job Description:
About the Role -
As a Senior Physical Design Engineer (Interconnects), you will be responsible for the physical design implementation of the high-speed logic that binds the SoC together. This includes scalable Network-on-Chips (NoC), coherent CPU clusters, and critical Uncore subsystems.
In this role, you will move beyond standard block-level implementation to tackle the unique challenges of high-speed Interconnects. You will bridge the gap between RTL design and physical design, ensuring that our complex interconnect architectures achieves aggressive PPA (Power, Performance, Area) targets on the world’s most advanced process nodes.
Responsibilities - What You’ll DoEnd-to-End Execution: Own the RTL-to-GDSII implementation of complex System IP components, including NoC fabrics, coherent clusters, and memory subsystem logic.
IP-Physical Co-Design: Partner with design/architecture from early-stage feasibility analysis to IP convergence. You will help identify and resolve physical bottlenecks—such as long-wire delays or routing congestion—by suggesting microarchitectural tweaks or optimized pipelining.
System-Level Floorplanning: Develop and refine floorplans for implementing massive, bus-heavy subsystems.
Interconnect Problem Solving: Solve physical challenges unique to system-level integration, such as closing timing on wide, high-frequency buses, managing global clock distribution etc.
Methodology & Automation: Execute and improve automated design flows for synthesis, place-and-route, and sign-off. You will contribute to internal scripts and methodologies to streamline implementation.
Relevant Experience: 4+ years of hands-on physical design experience, with a focus on closing high-performance blocks in FinFET nodes (7nm or below).
System IP Knowledge: Solid understanding of SoC building blocks such as NoC architectures, coherent interconnects, or cache-coherent clusters. You should be comfortable reading RTL to understand design intent.
Physical Implementation Skills: Mastery of hierarchical design techniques, including partitioning, timing budgeting, and multi-mode multi-corner (MMMC) timing closure.
EDA Tool Proficiency: Strong hands-on proficiency with major EDA suites - Synopsys and/or Cadence implementation and sign-off tools.
Analytical Mindset: A data-driven approach to optimizing PPA trade-offs, combined with the ability to communicate technical challenges clearly to the cross-functional teams.
Education: BS or MS in Electrical Engineering, Computer Engineering, or a related field.
Shape the Ecosystem: Help build the RISC-V infrastructure that is redefining the global compute landscape.
Technical Versatility: Gain exposure to a wide array of IPs in our portfolio and opportunities to work across IPs and product lines.
Expert Collaboration: Join a fast-paced environment where innovation and technical ownership are at the heart of everything we do.
Additional Information:
This position requires a successful background and reference checks and satisfactory proof of your right to work in:
IndiaAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.
SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.
Skills Required
- 4+ years of hands-on physical design experience
- Experience closing high-performance blocks in FinFET process nodes at 7nm or below
- Understanding of NoC architectures, coherent interconnects, or cache-coherent clusters
- Ability to read RTL and understand design intent
- Expertise in hierarchical design, partitioning, timing budgeting, and MMMC timing closure
- Hands-on proficiency with Synopsys and/or Cadence implementation and sign-off tools
- Data-driven PPA optimization and clear technical communication skills
- BS or MS degree in Electrical Engineering, Computer Engineering, or a related field
- Successful background and reference checks
- Authorization to work in India
- Authorization to access export-controlled technology, or ability to obtain required export licenses or approvals
What We Do
The heart of SiFive is RISC-V! SiFive creates the building blocks of RISC-V-based IP that are the inevitable innovative reimagining of every computing platform.
