Top Design Engineer Jobs in Bangalore

Perform functional verification of CPU logic: develop verification plans, testbenches, and environments; run simulations, emulate and FPGA validate designs; root-cause and debug failures; collaborate with architects, RTL and physical design teams; document plans and improve verification infrastructure and methodology.

The Senior Design Quality Engineer ensures quality and reliability in medical products by leading quality strategy, managing risk, and collaborating across teams for product improvement.

The Staff Engineer will lead digital design engineering efforts, mentor junior engineers, and develop specifications and RTL design while also collaborating with verification teams and supporting post-silicon activities.

The role involves leading the development of complex mixed Signal SoCs, focusing on high-speed designs, signoff implementations, and working with advanced technologies like 16 nm and 7 nm processes.

Responsible for verifying Design for Debug architecture, creating test cases and test benches using UVM. Coordinate cross-functional efforts for full coverage verification.

The Sr. SoC Design Verification Engineer is responsible for SoC architecture verification, creating test cases and test benches using UVM, coordinating efforts across teams to achieve verification goals.

The Staff Engineer will design and optimize GaN semiconductor devices, handle TCAD simulations, and collaborate cross-functionally to improve product design and reliability.

Lead the development of power management ICs, resolve technical challenges, and optimize designs for performance and reliability. Collaborate with cross-functional teams and drive product development with innovative ideas.

The Senior Engineer will collaborate with design teams, integrate verification processes, ensure silicon success, and assist with various tasks. Key responsibilities include problem-solving, debugging, and sharing expertise with team members.

Lead block-level designs and verification of complex digital systems while mentoring junior engineers and optimizing performance and power efficiency.

Design and deliver high-speed DDR IO circuit blocks for next-generation memory in advanced CMOS nodes. Perform powerbus and jitter analysis, timing closure, and collaborate with layout, verification, and cross-functional teams. Propose innovative IO design solutions and methodologies, and support analog/mixed-signal custom design, calibration, and clocking circuit work.

Design and deliver electrical control panel projects end-to-end: interpret customer requirements, produce FDS, wiring/single-line diagrams, panel layouts and BOMs; perform power and heat calculations, system testing, support FAT and commissioning; ensure IEC/JIC compliance, report progress, mitigate technical risks, and share best practices.

The role involves performing timing analysis and optimization for SoC designs, collaborating with cross-functional teams to ensure efficiency, functionality, and performance in high-performance, low-power designs.

The role involves executing physical design flows, performing synthesis, floor-planning, timing closure, power optimization, and verification for ASIC/SoC blocks in audio applications.

This role involves executing electrical engineering activities, developing diagrams, performing sizing calculations, and supporting commissioning and troubleshooting for industrial projects.

Lead complex digital design projects, providing technical leadership and mentoring engineers while influencing product direction and methodology improvements.

Design, simulate, verify, and optimize analog and mixed-signal circuits for advanced process nodes. Create floorplans, extract parameters, develop test plans, analyze results against power/performance/area/timing/yield goals, and collaborate with cross-functional teams to resolve issues.

Design, develop, and verify analog and mixed-signal circuits for advanced process nodes. Create floorplans, extract chip parameters, simulate analog behavior, develop and execute test plans, analyze results for power, performance, area, timing, and yield, and collaborate with cross-functional teams to resolve design issues and optimize circuits.

Responsible for full-chip and subsystem physical design (RTL-to-GDSII) for large SoCs across 40nm–3nm nodes. Tasks include floorplanning, place-and-route, CTS, timing closure, extraction, IR/EM checks, DRC/LVS, signal integrity, IP integration, methodology/flow ownership, mentoring junior engineers, and coordinating with global teams to achieve first-pass silicon.

Develop and execute verification strategies and UVM-based testbenches for IP blocks in SoCs/FPGAs. Create directed and constrained-random tests, SVA assertions, and formal checks; run regressions, debug failures, track coverage metrics, and automate verification flows with scripting.

Lead the RTL design for PCIe/CXL subsystems, collaborating with teams for architecture, validation, and integration. Mentor juniors and drive design quality improvements.

The Principal Engineer will design high-performance analog/mixed-signal IP, leading implementations and collaborating across teams, while providing technical leadership and validation support.

Lead physical design for 32-bit microcontrollers and wireless solutions: implement P&R flows, timing closure and clock tree synthesis, floorplanning for multi-voltage islands, power network and EM/IR analysis, automate flows, ensure PV compliance, and collaborate with vendors and global teams.

Lead functional verification for complex IP and SoC designs using UVM/SystemVerilog and SVA. Develop test plans, reusable verification components, automation and formal checks; debug failures, drive coverage closure, collaborate with RTL and post-silicon teams, and mentor junior engineers.

Responsible for software development related to IP blocks, defining HW/SW interfaces, collaborating with HW engineers, and ensuring efficient programmability and usability for software consumption. Involves pre-silicon validation and development of drivers and firmware prototypes.