Top Design Engineer Jobs in Bangalore

Lead Analog IC design team to develop high-speed multiplexers and switches, overseeing project advancements and ensuring technical objectives are met.

Looking for a Digital IC Design Engineer with 3-5 years of experience in RTL design for ASICs or SoCs, focusing on digital logic design using Verilog, VHDL, and System Verilog, collaborating with teams for design and verification.

The Analog IC Design Engineer will specialize in RF transceiver design, focusing on architecture, schematic, layout design, and validation phases. Responsibilities include PLL and clock system design, transmitter design, and ensuring effective collaboration with stakeholders.

Design and develop analog integrated circuits, utilizing AI/ML tools. Collaborate with teams, conduct simulations, and drive innovation in circuit design.

The Senior Analog Physical Design Engineer will lead layout efforts, collaborating across teams, conducting layout reviews, and mentoring contract engineers to ensure project success.

The Analog IC Design Engineer will work on RF transceiver products, participating in the complete design cycle including architecture, schematic design, layout, and validation. Responsibilities include designing RF blocks and calibration modules, while collaborating with various stakeholders to ensure project success.

Lead SoC Front End team to integrate complex ARM architecture, collaborate with various teams for feature updates, and ensure power intent and testability in SoC designs.

Lead an Analog IC design team, guide design processes, collaborate with cross-functional teams, and ensure product development from definition to manufacturing.

The Senior Principal Digital IC Design Engineer will lead project activities, mentor engineers, architect and benchmark MCU and DSP systems, and improve design methodologies.

Design and develop analog IP blocks for power management, oversee block-level design and simulation, and work with various engineering teams for implementation and validation.

The Lead Design Engineer will work on Verilog coding, RTL design, timing constraints, and simulation testing, while being familiar with various protocols.

Lead the physical design for NVM IPs, overseeing RTL to GDS flow, automation of design processes, and mentoring junior engineers.

Lead SoC design and integration for next-generation networking DPUs and switch silicon. Define system-level methodologies, drive cross-functional SOC milestone execution, integrate subsystem pieces, and deliver models for verification across cluster/sub-system/SOC/emulation levels while collaborating with software and physical-design teams.

Design and implement SoC units by defining micro-architecture, developing RTL, collaborating with verification and physical design teams, owning silicon bring-up, and mentoring junior engineers.

Design and implement micro-architectures in RTL for memory subsystems, verify functionality, and collaborate with cross-functional teams for debugging and synthesis.

Develop and optimize mixed-signal and high-speed IPs, including RTL coding and simulation for full-chip designs, while collaborating across teams.

This role involves executing electrical engineering activities, developing diagrams, performing sizing calculations, and supporting commissioning and troubleshooting for industrial projects.

The role involves executing physical design flows, performing synthesis, floor-planning, timing closure, power optimization, and verification for ASIC/SoC blocks in audio applications.

Assist in the electrical design of electrolyzer test stations, develop schematics, support CAD modeling, and collaborate with mechanical engineers.

Lead PCIe/CXL subsystem micro-architecture, RTL implementation, integration, and sign-off. Collaborate with architecture, verification, physical design, DFT, firmware, and validation teams. Support silicon bring-up, post-silicon debug, drive coding best practices, and mentor junior designers.

Lead system-level digital architecture and design for DSP datapaths and control blocks. Drive methodology improvements, mentor engineers, lead small technical teams, collaborate cross-functionally, engage customers, and influence product roadmaps.

Design and verify analog I/O circuits (GPIOs, level shifters, LVDS, bandgaps, LDOs), run PVT and Monte Carlo simulations, perform post-layout simulations, analyze verification data, generate dotlibs/IBIS, and collaborate cross-functionally for SoC integration.

Lead RTL and microarchitecture design for Cerebras Wafer Scale Engine: author functional specs, develop RTL, synthesize, integrate third-party IP, collaborate with PD, verification and software teams, debug silicon-level functional/timing/power issues, and drive PPA and test/bring-up activities.

Lead complex digital design projects, providing technical leadership and mentoring engineers while influencing product direction and methodology improvements.

Verify ASIC design, architecture and micro-architecture of memory subsystem IPs. Define verification scope, develop test plans, infrastructure, BFMs, monitors, checkers and scoreboards. Use coverage-driven methodologies (SystemVerilog/UVM/VMM), assertions, random stimulus, and functional coverage. Collaborate with architects, designers and pre/post-silicon teams to achieve verification closure.