Top Design Engineer Jobs in Bangalore

Lead and own analog IC product design from definition through production. Manage and mentor a design team, guide circuit design and silicon evaluation, coordinate layout, verification, validation, and production transfer, collaborate with systems, applications, marketing and customers, and participate in hiring and personnel development.

Design and implement FPGA prototypes for ASIC validation, feature development, and high-speed interface verification. Develop Verilog RTL, integrate complex IP and memory interfaces, perform synthesis, place-and-route, timing closure, optimization, and hardware debugging. Lead board bring-up and validation, automate build and regression flows with Python, Tcl, or Bash, and collaborate with architecture, verification, firmware, and post-silicon teams to resolve issues and improve FPGA methodology.

Design and verify high-speed mixed-signal communication and high-performance digital circuits. Responsibilities include RTL coding, simulation, synthesis, timing closure, verification, debugging, test method/spec preparation, documentation support, and cross-functional collaboration with analog and digital teams to deliver communication chips.

Design and verify custom circuit IPs (SRAM, analog/digital) to improve power, performance, silicon correlation and security for NVIDIA chips. Architect circuit solutions, run SPICE and timing simulations, develop flows (EM/IR/Noise/STA), collaborate globally, and mentor junior engineers.

Designs and verifies technical drawings for customized products, develops bills of materials and assembly instructions, supports manufacturing and sales, reviews designs for quality, coordinates engineering orders, manages SAP item creation and long-lead items, and ensures customer requirements are met before manufacturing release. The role also supports cost estimation, technical clarifications, project planning, reporting, and collaboration with production, sales, customers, and internal teams.

Develops high-speed IC packages from concept through tapeout, including C4 and BGA ball maps, netlist mappings, die placement, padstacks, connectivity, and package requirement documents. Collaborates with architecture, chip, board, manufacturing, and simulation teams to optimize signal and power integrity, manufacturability, reliability, thermal performance, and cost. Supports advanced packaging architectures, design-flow development, library maintenance, and scripting automation.

Lead high-speed IC package development from concept through tapeout. Develop C4 and BGA ball maps, netlist mappings, die placement, padstacks, connectivity, and package requirement documents. Optimize package designs for signal and power integrity, manufacturability, reliability, thermal and mechanical constraints, and cost. Collaborate with chip, board, architecture, manufacturing, and simulation teams while contributing to design tools, processes, libraries, and automation.

Lead architecture, design, and verification of mixed-signal digital IP (e.g., ADCs, DACs, PLLs) for automotive, industrial, and medical SoCs. Drive CMOS/SOI designs and reusable IP, lead small teams, contribute to SoC integration, DFT strategies, and documentation. Collaborate with test, product, and applications engineering to ensure production release and propose innovative technical solutions.

Lead architecture, design, and verification of mixed-signal and digital IP (DAC/ADC/PLL, wireless interfaces). Drive CMOS/SOI designs, lead small teams, support SoC integration, DFT strategies, documentation, and partner with test/product teams for production release.

Designs analog layouts from block level through full chip for power-management products, including charge pumps, comparators, amplifiers, bandgaps, and regulators. Owns floorplanning, matching, electromagnetic and reliability design, DRC/LVS flows, package integration, and die-to-bump connectivity. Collaborates with circuit and layout teams, drives methodology and portability improvements, and mentors engineers while potentially managing a small team.

Leads physical design implementation for complex SoCs from RTL to GDSII across advanced technology nodes. Responsibilities include floorplanning, place and route, clock-tree synthesis, timing closure, physical verification, IP integration, IR/EM analysis, signal integrity, and methodology development. The role owns full-chip and subsystem challenges, collaborates with global implementation teams, mentors junior engineers, and supports first-pass silicon success. Occasional travel is required.

Design, model, and integrate electromechanical systems including PCBA enclosures and cabling. Manage design lifecycle from concept to DVT, create sheet metal and complex assembly drawings, perform mechanical calculations, use PLM (Team Center), follow ECN/ECR and DFMEA processes, and coordinate cross-functional teams. Provide technical project management and travel when required.

Design and validate high-performance I/O circuits (GPIO, LVDS, DDR, SerDes support) at transistor level. Perform pre/post-layout simulation, signal integrity and ESD analysis, layout reviews, silicon bring-up, characterization, and cross-functional collaboration to deliver production-ready IO IP.

The Physical Design Engineer will perform synthesis, timing closure, and integration tasks, collaborating with the RTL team to optimize design flow.

Lead and execute physical design activities for semiconductor blocks: floorplanning, placement, clock-tree synthesis, routing, timing closure, power optimization, and signoff. Collaborate with RTL, timing, and verification teams, drive timing convergence, resolve DRC/LVS issues, and mentor junior engineers to deliver tapeout-ready layouts.

Lead early GPU floorplanning and SOC planning, collaborating with architects and physical design teams to optimize area, timing, congestion, power/clock distribution, packaging and P&R. Perform feasibility studies, influence early implementation decisions, drive area reviews, and build tools/infrastructure to improve chip area and execution speed.

Design and own micro-architecture and RTL for memory subsystem / interconnect IP, implement synthesis/timing-clean RTL, collaborate with architects, verification, timing/VLSI, FPGA/SW prototyping, and perform post-silicon debug.

Leads CPU circuit design for SRAM, register files, memory compilers, datapaths, and caches. Responsibilities include floorplanning, circuit optimization for power, performance, area, timing, and yield, simulation, verification, design-flow automation, and resolving pre- and post-silicon issues. Manages and mentors circuit design engineers, sets technical strategy, collaborates with architecture, RTL, physical design, layout, and verification teams, and drives reliable semiconductor solutions.

Design and verify mixed-signal and digital IP (DAC, ADC, PLL, wireless interfaces) for automotive, industrial, and medical SoCs. Define architecture, lead small teams, drive CMOS/SOI implementation, collaborate on DFT and SoC integration, and support production release with thorough documentation and testing.

Design, implement, and debug FPGA-based prototypes for ASIC validation and prototyping. Develop RTL in Verilog/SystemVerilog, integrate high-speed IPs (PCIe, DDR/LPDDR, Ethernet, CXL, HBM), perform synthesis/place-and-route/timing closure, and create automation scripts. Collaborate with architecture, verification, firmware, and post-silicon teams to resolve functional and performance issues and improve FPGA methodology and bring-up plans.

Design and implement high-performance ASIC blocks from specification through tape-out. Perform RTL development, timing and power optimization, formal and CDC verification, system debug, emulation, flow automation, and lab validation to achieve FCS.

Design and optimize sheet metal components and thermal systems for the e^pump with a focus on manufacturability and performance requirements.

The Sr. Mask Design Engineer will layout and verify analog and mixed signal circuits, using Cadence tools and collaborating with designers for optimal circuit performance.

Design and own transistor-level analog blocks (bandgap references, op-amps, comparators, level shifters), define architectures to meet specs, perform schematic capture, circuit simulation and Monte Carlo analysis, guide layout for performance, mentor junior engineers, and support silicon validation and I/O/ESD design for PMIC and DC-DC products.

Lead verification strategy and architecture, design scalable UVM/SystemVerilog testbenches, develop BFMs/monitors/scoreboards, write complex constrained-random tests, perform formal verification and GLS, analyze coverage metrics, debug root causes with design teams, mentor juniors, and provide verification sign-off to meet project schedules.