Top Design Engineer Jobs in Bangalore

Design and simulate transistor-level analog/mixed-signal IC blocks (amplifiers, converters, power circuits), define architectures, integrate blocks into mixed-signal systems, present results to teams/customers, support layout, lab evaluation and test, mentor others, and improve design methodologies to meet power, timing and functional objectives.

Design full-custom I/O and analog mixed-signal layouts in planar and FinFET processes; drive floorplanning and power/IO planning; perform comprehensive layout verification (DRC/LVS/ANT/ERC/DFM, LPE, PERC, EM/IR); own end-to-end deliverables, mentor juniors, and collaborate across sites to meet schedules and quality targets.

Design and deliver high-quality memory layouts for advanced FinFET processes. Manage floor-planning, schedule, and chip integration; perform physical verification (LVS/DRC/ERC/Antenna/EM); lead and train layout teams; document methodologies and adapt to new process rules and automation.

Design full-custom I/O and analog mixed-signal layouts in planar and FinFET technologies, own end-to-end deliverables, drive floorplanning and power/IO planning, perform comprehensive layout verification (DRC/LVS/ANT/ERC/DFM, extraction, EM/IR), debug layouts, and lead/train junior engineers while coordinating across sites.

Design and verify custom circuit IPs (SRAM, analog/digital) to improve power, performance, silicon correlation and security for NVIDIA chips. Architect circuit solutions, run SPICE and timing simulations, develop flows (EM/IR/Noise/STA), collaborate globally, and mentor junior engineers.

Design and verify high-speed mixed-signal communication and high-performance digital circuits. Responsibilities include RTL coding, simulation, synthesis, timing closure, verification, debugging, test method/spec preparation, documentation support, and cross-functional collaboration with analog and digital teams to deliver communication chips.

Lead micro-architecture and RTL development and HW/SW co-design for SoC and IP (memory controllers, PCIe, CXL). Collaborate with architects and verification teams to deliver high-performance, timing-critical designs through front-end flow, timing closure, and power optimization.

Lead architecture, design, and verification of mixed-signal and digital IP (DAC/ADC/PLL, wireless interfaces). Drive CMOS/SOI designs, lead small teams, support SoC integration, DFT strategies, documentation, and partner with test/product teams for production release.

Lead architecture, design, and verification of mixed-signal digital IP (e.g., ADCs, DACs, PLLs) for automotive, industrial, and medical SoCs. Drive CMOS/SOI designs and reusable IP, lead small teams, contribute to SoC integration, DFT strategies, and documentation. Collaborate with test, product, and applications engineering to ensure production release and propose innovative technical solutions.

Lead hardware engineer for product design, developing specifications, schematics, and layouts, collaborating with teams, performing validations, and transitioning to production.

Design and develop micro-architecture for memory sub-system components, collaborating with architects and verification teams to ensure performance and correctness.

Lead Test and DfT Engineers in defining and implementing testing techniques for digital, analog, and mixed-signal products, focusing on cost optimization and standardization.

As a DFT Design Engineer, you will enhance test coverage and manufacturability, developing DFT architectures and working with cross-functional teams to ensure testing of silicon solutions.

Designs RTL for FPGAs and ASICs, develops logic, simulates and verifies IP blocks and subsystems, defines microarchitecture, prototypes models, and collaborates with physical implementation and verification teams to meet power, performance, and area goals.

Lead full RTL-to-GDS physical design for custom IP and SoC products: synthesis, floorplanning, place-and-route, clock tree synthesis, timing closure, power/noise and reliability analysis, signoff verification, PPA optimization, and methodology automation.

Lead memory layout design for advanced submicron processes using Cadence and Calibre tools. Own floor-planning, hierarchy layout, verification (LVS/DRC/ERC), scheduling, team leadership, and integration. Document methodologies and adapt flows for new process nodes while training junior engineers and ensuring on-time, high-quality deliverables.

Lead SoC design activities including microarchitecture specification, RTL coding, CDC and lint closure, SoC integration (clocking/resets), synthesis and timing closure, PPA trade-offs, and post-silicon debug while collaborating with architecture, verification, and physical design teams.

Design, develop, and simulate analog and mixed-signal circuits for advanced process nodes. Create floorplans, extract parameters, run tests, verify performance/power/area/timing/yield, and collaborate with architecture and layout teams to resolve design challenges and drive continuous improvement.

Perform full-custom analog/mixed-signal IC layout in advanced foundry nodes (2nm-7nm+); own physical verification (DRC/LVS/density/tape-out checks); resolve complex layout issues; optimize for performance, area and manufacturability; mentor junior engineers; collaborate cross-functionally and represent the team in technical discussions.

The Physical Design Engineer will perform synthesis, timing closure, and integration tasks, collaborating with the RTL team to optimize design flow.

Lead and execute physical design activities for semiconductor blocks: floorplanning, placement, clock-tree synthesis, routing, timing closure, power optimization, and signoff. Collaborate with RTL, timing, and verification teams, drive timing convergence, resolve DRC/LVS issues, and mentor junior engineers to deliver tapeout-ready layouts.

Design and own RTL micro‑architecture for digital control blocks in high‑speed mixed‑signal PHYs. Define digital/analog interfaces, implement calibration algorithms, ensure protocol/IP compliance (PIPE), drive front‑end closure (lint/CDC/formal/STA), collaborate with AMS and DV teams, and support post‑silicon bring‑up and debug.

Design and deliver RTL for mixed-signal DDR PHY IPs using SystemVerilog; define architecture/microarchitecture, implement RTL, set up front-end automation and tool flows (lint, CDC, RDC, synthesis), ensure RTL quality, optimize area/power with UPF/clock gating, and collaborate with validation, backend, and SoC teams while driving tooling and methodology improvements.

Lead early GPU floorplanning and SOC planning, collaborating with architects and physical design teams to optimize area, timing, congestion, power/clock distribution, packaging and P&R. Perform feasibility studies, influence early implementation decisions, drive area reviews, and build tools/infrastructure to improve chip area and execution speed.

Design and own micro-architecture and RTL for memory subsystem / interconnect IP, implement synthesis/timing-clean RTL, collaborate with architects, verification, timing/VLSI, FPGA/SW prototyping, and perform post-silicon debug.