Top Design Engineer Jobs in Bangalore

The role involves defining and implementing digital blocks, collaborating with teams, scripting for automation, and contributing to debugging and communication efforts.

The Staff Analog Design Engineer will manage analog IP design and development for power management products, ensuring technical quality from definition to delivery, while collaborating with multiple teams on validation and performance measurement.

The Principal Analog Design Engineer leads the design and development of power management analog IP blocks, ensuring successful transfer to production and collaboration across teams.

The Staff Digital Design Engineer will lead digital design architecture, RTL implementation, and collaborate with multidisciplinary teams to develop Power Management ICs, ensuring high quality and performance.

The role involves leading digital design architecture, RTL implementation, trade-off analysis, and collaborating with global teams on ASIC development projects. Responsibilities include enhancing design methodologies and managing multiple projects within the team.

Design and develop analog IP blocks for power management products, collaborating with teams on verification and execution while guiding layout processes.

Design and develop analog IP blocks for power management, oversee block-level design and simulation, and work with various engineering teams for implementation and validation.

The Staff Digital Design Engineer leads digital design projects, influences product direction, mentors engineers, and guides best practices across multiple technical domains.

Design high-speed D2D and SERDES products, develop analog/mixed signal IC circuit blocks, collaborate on circuit design and verification.

The Senior Hardware Design Engineer will lead complex hardware designs, mentor engineers, and make key technical decisions in networking systems.

Lead hardware design for advanced networking platforms, define architecture, guide design standards, and mentor engineers in system-level solutions.

As a Senior Engineer in ASIC Design, you'll develop and document ASIC IP blocks, optimize design methodologies, and collaborate on cutting-edge 5G and 6G technologies.

The role involves ownership and design of analog sub-blocks in high-speed PHYs, mentoring junior engineers, and collaborating on complex circuit designs.

Design complex ASIC memory subsystem components in collaboration with architects and verification teams, focusing on micro-architecture, RTL development, and post-silicon verification.

The Senior SoC Logic Design Engineer will design and develop SoC solutions, oversee RTL coding and simulation, and ensure integration and quality of designs for various applications.

The role involves leading VLSI design engineering, overseeing project schedules, and developing complex test benches and verification methodologies.

Lead DFT ownership across projects: define test architecture, implement RTL DFT changes, perform scan insertion/LEC/CLP checks, develop test-mode timing constraints, run ATPG and timing simulations, implement/verify boundary-scan, ACJTAG, IEEE1500 and IEEE1687 (iJTAG) ICL/PDL, support post-silicon bring-up, and interact with customers and pre-sales.

Lead and execute functional verification for complex VLSI designs using SystemVerilog and UVM. Plan environments, generate test plans, develop verification environments, drive projects from concept to verification closure, and mentor teams. Prior memory IP (DDR/HBM/GDDR) verification experience is a plus.

Lead design verification efforts using SystemVerilog and UVM: plan verification environments and test plans, develop functional verification environments, verify complex designs, and drive projects to verification closure. Memory IP (DDR/HBM/GDDR) experience is a plus.

The Lead Design Engineer will code in RTL, create datapath designs, and manage complex FIFO design while collaborating with analog design teams.

Lead Test and DfT Engineers in defining and implementing testing techniques for digital, analog, and mixed-signal products, focusing on cost optimization and standardization.

The Engineer will design analog blocks, oversee their integration, mentor junior staff, and ensure quality layouts. Extensive experience with simulation and verification is required.

Lead SoC Front End team to integrate complex ARM architecture, collaborate with various teams for feature updates, and ensure power intent and testability in SoC designs.

The role involves leading RTL design for DDR/LPDDR/HBM subsystems, collaborating on architecture, verification, and physical design, mentoring junior staff, and improving design quality.

The Principal Design Engineer will design high-speed analog and mixed-signal circuits, lead design reviews, and drive micro-architecture innovations for HBM PHY products.