The Lead Analog Design Engineer will take a Key role on the Analog and Mixed signal design team as part of a Die to Die Product Development Team.
Job Responsibilities:
- Design of High Speed D2D and SERDES products at industry standard data rates up on leading edge technology nodes (e.g. 3nm FinFET CMOS)
- Design and development of analog/mixed signal IC circuit blocks from initial concept/specification through final verification of conformance to customer specifications
- Work closely with Layout Design Engineers to design IC circuit blocks and PMA sections
- Work with Technical Team Leads in the areas of circuit design and SERDES architectures
- Work with global teams (US, west coast and east coast), which work in different time-zones
Job Qualifications:
- BEng, MEng, PhD or equivalent.
- Candidate’s background should include a minimum of 8 years of CMOS design experience, preferably in the area of CMOS SERDES or high-speed I/O IC design
- Should have a good understanding of jitter and signal equalization techniques
- Design experience in some of the following SERDES circuit blocks: Driver, Receiver, Serializer, Deserializer, Phase Interpolator, Low jitter PLL, High Speed Clock Distribution, Bias and Bandgap, Voltage Regulators
- Excellent problem-solving skills, analog aptitude, good communication skills and ability to work cooperatively in a team environment
- Position requires proficiency in using CAD tools for circuit simulation, layout and physical verification
Additional Skills/Preferences:
- Cadence tool experience is desirable and design experience at >10Gbps and in <16nm technologies
- Lab test experience as part of silicon evaluation is advantageous
Skills Required
- BEng, MEng, PhD or equivalent
- Minimum of 8 years of CMOS design experience
- Experience in CMOS SERDES or high-speed I/O IC design
- Good understanding of jitter and signal equalization techniques
- Design experience with SERDES circuit blocks (Driver, Receiver, Serializer, Deserializer, Phase Interpolator, Low jitter PLL, High Speed Clock Distribution, Bias and Bandgap, Voltage Regulators)
- Proficiency using CAD tools for circuit simulation, layout and physical verification
- Excellent problem-solving, analog aptitude, communication and teamwork skills
- Cadence tool experience
- Design experience at >10Gbps and in <16nm technologies
- Lab test experience as part of silicon evaluation
Cadence Design Systems Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.
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Equity Value & Accessibility — A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
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Healthcare Strength — Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
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Leave & Time Off Breadth — Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.
Cadence Design Systems Insights
What We Do
Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.
