Top Design Engineer Jobs in Bangalore

The role involves design authority responsibilities in AC & DC Drive Cabinet Engineering, utilizing design tools for system integration and project execution, focusing on compliance with IEC and IS standards.

Design and develop micro-architecture for memory sub-system components, collaborating with architects and verification teams to ensure performance and correctness.

The role involves translating system requirements into hardware specifications, digital design, RTL coding, and collaborating with verification and physical design teams.

The Physical Design Engineer will perform synthesis, timing closure, and integration tasks, collaborating with the RTL team to optimize design flow.

As a Memory Mask Design Engineer at NVIDIA, you'll implement high-performance CMOS integrated circuit layouts, specifically for digital memory, while using advanced EDA tools and following industry standards.

Design and implement complex analog circuits for advanced DRAM products, oversee layout processes, validate designs, and mentor junior engineers. Collaborate across multiple teams to enhance product manufacturability using AI tools.

Design and optimize structural and thermal components for the e^pump, ensuring manufacturability while meeting safety requirements. Collaborate with teams on refining designs based on feedback and validate product performance through comprehensive testing and analysis.

Lead end-to-end physical implementation of major IP blocks or full-chip designs: floorplanning, place-and-route, clock tree synthesis, timing closure, physical verification, and automation of flows. Collaborate with RTL, DFT, verification, package, and library teams to meet PPA targets, mentor junior engineers, and drive manufacturability and sign-off across PVT corners.

The Analog Flash Design Engineer will design and verify analog/mixed-signal circuits for embedded Flash Memory, collaborating with cross-functional teams, optimizing performance, and contributing to innovation.

The role involves developing and testing customized DSP instructions for AI and video processing applications, optimizing algorithms, and collaborating with hardware teams.

The IO Mixed Signal Design Engineer will integrate and verify mixed signal blocks in FPGA's, develop analog circuits for IO applications, work with design requirements, optimize circuits, and support post-tapeout phase.

The Principal IO Mixed Signal Design Engineer will integrate and verify mixed signal blocks in high-speed IOs for FPGAs, develop custom circuits, and support post-tapeout phases.

Lead the physical design for NVM IPs, overseeing RTL to GDS flow, automation of design processes, and mentoring junior engineers.

The Sr. Mask Design Engineer will layout and verify analog and mixed signal circuits, using Cadence tools and collaborating with designers for optimal circuit performance.

Design and optimize sheet metal components and thermal systems for the e^pump with a focus on manufacturability and performance requirements.

Lead physical design and implementation of semiconductor circuits, mentor engineers, ensure timely product delivery, and optimize design methodologies.

The Senior Analog Physical Design Engineer will lead layout efforts, collaborating across teams, conducting layout reviews, and mentoring contract engineers to ensure project success.

Lead and manage a digital design team to define microarchitecture and implement digital components for power management ICs (PMICs). Oversee RTL, gate-level design, power-aware design, CDC, verification, silicon debug, DFT and integration with analog blocks; mentor staff and align team objectives with company strategy to deliver production-ready chips.

The Lead Design Engineer will work on Verilog coding, RTL design, timing constraints, and simulation testing, while being familiar with various protocols.

Design and implement micro-architectures in RTL for memory subsystems, verify functionality, and collaborate with cross-functional teams for debugging and synthesis.

Responsible for end-to-end verification of IOMMU IP in a hybrid role, ensuring functional correctness, debugging, and driving coverage closure.

The engineer is responsible for physical implementation from RTL to GDS, including design optimization, verification, and collaboration with teams. Requires 8+ years of experience.

Develop and optimize mixed-signal and high-speed IPs, including RTL coding and simulation for full-chip designs, while collaborating across teams.

Assist in the electrical design of electrolyzer test stations, develop schematics, support CAD modeling, and collaborate with mechanical engineers.

Lead functional verification for complex IP blocks and SoC designs: create test plans and UVM environments, build reusable verification components, implement SVA and coverage-driven closure, develop automation tools, debug and perform root-cause analysis, collaborate with cross-functional teams, and mentor junior engineers.