Broadcom

Memory Design Engineer

Posted 24 Days Ago

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Hiring Remotely in Electronics City, Bangalore, Karnataka, IND

Remote

Junior

Software • Semiconductor • Manufacturing

The Role

Design and develop single- and multiport SRAM and register-file memory compilers across advanced process nodes. Responsibilities include CMOS circuit design, simulation, timing and margin analysis, statistical yield characterization, power and signal-integrity analysis, compiler sign-off, silicon failure diagnosis, and layout debugging. The role also involves power-gating and split-rail architectures, memory DFT considerations, and use of circuit simulation, schematic, layout, and scripting tools.

Summary Generated by Built In

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Job Description:

JD for Memory Design Engineer

1) Contribute/Lead towards Design and Development of Single/Multiport SRAM, Register file compilers in 28nm/16FF/7FF/5FF Technologies
2) Circuit design/simulation of key components such as bitcell, WL decoder, SAMP, Column decoder and control logic.
3) Development of critical path and characterization flow to perform detailed margin and characterization simulations.
4) Statistical Analysis of Bit-Cell and Sense Amplifier and Self Time Blocks for Compiler Target yield Sign-Off
5) Design Tuning, Margin Analysis and Sign-Off for Complete Compiler to meet Yield and Performance targets.
6) Logic simulations and detailed timing analysis of key paths in high speed memory design.
7) Signal-Integrity (EM) and Power-Integrity (IR drop) analysis and design.

Skill Sets/Prerequisites

1) Expertise of high speed/low power CMOS circuit design, clocking scheme, Static and dynamic logic circuits
2) Experience in Designing and driving one or many Memory Compilers Specifications to final release
3) Deep expertise in Understanding and Developing Split rail, Power gating Architecture and circuit design
4) Hands on Experience on Silicon Debug/Diagnose the failures. Deep expertise on Silicon Failures, Analysis and fixing.
5 Complete hands on experience in using Cadence/Mentor schematic/layout editor tools
6) Complete hands on experience with Circuit simulation, MC analysis and waveform viewer tools such as HSPICE, HSIM, XA, FinSim, XARA, nWave, waveform viewer etc
7) Experience in Skill/Perl/Python Scripting is a strong plus
8) Experience in Understanding the layout design issues in sub nanometer regime is a must.
9. Expertise in Understanding Memory DFT is a Plus.
10. Masters Degree with 2+ Years or Bachelors Degree with 3+ years

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Skills Required

Master’s degree with at least 2 years of relevant experience, or bachelor’s degree with at least 3 years of relevant experience
Expertise in high-speed and low-power CMOS circuit design
Experience with clocking schemes and static and dynamic logic circuits
Experience designing and driving memory compiler specifications through final release
Expertise in split-rail and power-gating architecture and circuit design
Hands-on experience debugging and diagnosing silicon failures
Hands-on experience with Cadence and Mentor schematic/layout editor tools
Hands-on experience with circuit simulation, Monte Carlo analysis, and waveform viewer tools
Understanding of layout design issues in sub-nanometer technologies
Experience with Skill, Perl, or Python scripting
Expertise in memory DFT

Broadcom Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Broadcom and has not been reviewed or approved by Broadcom.

Equity Value & Accessibility — Equity is used broadly through RSUs with quarterly or annual vesting, and an ESPP with a discount and look‑back that can add meaningful upside. Company disclosures show ongoing equity grants, including inducement RSUs tied to acquisitions, underscoring equity’s central role in total rewards.
Retirement Support — A 401(k) plan with a competitive company match and immediate vesting is consistently highlighted, supporting long‑term savings. Tax‑advantaged accounts like HSA/FSA further strengthen the financial wellness toolkit.
Pay Growth & Progression — Compensation ceilings in technical tracks are described as high, with wide ranges and very strong totals for experienced engineers. Sales compensation is also characterized as competitive, supporting attractive on‑target earnings.