Sr Principal Design Engineer

Reposted 18 Days Ago
Be an Early Applicant
Bangalore, Bengaluru Urban, Karnataka, IND
In-Office
Senior level
Artificial Intelligence • Cloud • Hardware • Software • Semiconductor
The Role
Lead and execute functional verification for complex VLSI designs using SystemVerilog and UVM. Plan environments, generate test plans, develop verification environments, drive projects from concept to verification closure, and mentor teams. Prior memory IP (DDR/HBM/GDDR) verification experience is a plus.
Summary Generated by Built In
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
  • BE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer

  • 12+ years of Design Verification experience with SV/UVM

  • Strong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must.

  • Design Verification experience verifying complex designs and leading projects from concept to verification closure.

  • Strong hands-on UVM and System Verilog coding experience and functional verification environment development is required.

   Prior experience in IP verification of memory IP (DDR/HBM/GDDR) would be an added advantag

We’re doing work that matters. Help us solve what others can’t.

Skills Required

  • BE/BTech/ME/MTech in Electrical/Electronics/VLSI with experience as a design and verification engineer
  • 12+ years of design verification experience with SystemVerilog and UVM
  • Strong background in functional verification fundamentals, environment planning, and test plan generation
  • Experience verifying complex designs and leading projects from concept to verification closure
  • Hands-on UVM and SystemVerilog coding experience and functional verification environment development
  • Prior experience in IP verification of memory IP (DDR/HBM/GDDR)

Cadence Design Systems Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.

  • Equity Value & Accessibility A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
  • Healthcare Strength Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
  • Leave & Time Off Breadth Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.

Cadence Design Systems Insights

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The Company
HQ: San Jose, CA
8,216 Employees
Year Founded: 1988

What We Do

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.

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