MTS Digital Design Engineer

Responsibilities: 

OnSemi is seeking a Sr. Principal Digital design, NEW PRODUCT DEVELOPMENT, Power Management, to join our growing team in Bengaluru, India. This group is responsible for development of Power management products, LED drivers, SiC drivers, smart-Switches and efuses for consumer, industrial and automotive applications. In this role, you will focus on the following: 

• Work with different product lines for SoC RTL implementation of power driver digital controls for LED/SiC/smartFET/Efuse application, peripherals like I2C, SPI, LIN, CAN protocols 
• The candidate will work on digital design architecture, digital RTL, low power design, synthesis and timing analysis with PD engg, Physical Design (PD) interface for the power management chips 
• The candidate will be able to work as part of a large and focused team of engineers and will be able to collaborate successfully as needed with design architects, digital verification, project management, and digital and analog design teams in multiple worldwide geographies
• Define and implement micro-architecture to RTL implementation with the refining of features requirements throughout the design process
• Support the bring-up of various features at a system level in various pre-silicon platforms like SOCV, Emulation, FPGA.
• Own technical outcome of design, verification, implementation, and execution of Power Management ICs with complexities that can span from simple regulators to complex designs, control loops, and digital interfaces  
• Understand project goals, execute with realistic schedule, report status of progress  and understand clarity of project details and milestones 
• Lead and support Customer issues, Production issues, FW and System development, Failure Analysis
• Support post-silicon validation activities for your designs.

#LI-RG1

• Work with different product lines for SoC RTL implementation of power driver digital controls for LED/SiC/smartFET/Efuse application, peripherals like I2C, SPI, LIN, CAN protocols 
• The candidate will work on digital design architecture, digital RTL, low power design, synthesis and timing analysis with PD engg, Physical Design (PD) interface for the power management chips 
• The candidate will be able to work as part of a large and focused team of engineers and will be able to collaborate successfully as needed with design architects, digital verification, project management, and digital and analog design teams in multiple worldwide geographies
• Define and implement micro-architecture to RTL implementation with the refining of features requirements throughout the design process
• Support the bring-up of various features at a system level in various pre-silicon platforms like SOCV, Emulation, FPGA.
• Own technical outcome of design, verification, implementation, and execution of Power Management ICs with complexities that can span from simple regulators to complex designs, control loops, and digital interfaces  
• Understand project goals, execute with realistic schedule, report status of progress  and understand clarity of project details and milestones 
• Lead and support Customer issues, Production issues, FW and System development, Failure Analysis
• Support post-silicon validation activities for your designs.

#LI-RG1

Qualifications: 

• BS in Electrical Engineering or related + 14 years of experience, or MS + 12 years of experience in defining and implementing Digital Design, Architecture/u-Architectures and ASIC/Mixed signal SoC chip developments
• The ideal candidate should have thorough understanding of the end-to-end digital design flow in order to accurately and efficiently collaborate with all members of the technical staff, both analog and digital, regarding overall project development progress and status
• Solid understanding of RTL design, CDC, synthesis, timing analysis and CDC, UPF and system Verilog (assertion)
• Solid understanding of Verilog, TCL and Perl/Python/XML programming languages
• Experience in developing ASIC/Mixed signal ICs for various Power chips like LED/SiC/GAN drivers, SmartFET and Efuses. 
• Understanding of digital architecture trade-offs for power, performance, and area
• Solid track record of releasing complex ICs/ IPs to market 
• Goal and outcome-focused with the ability to handle multiple projects within the team 
• Ability to clearly articulate issues, challenges, and concerns to all levels of management 
• Must have good written and verbal cross-functional communication skills
• Experience with microprocessor interconnects and integrating peripherals into the interconnect

#LI-RG1