Top Design Engineer Jobs in Bangalore

Lead and execute backend digital physical design for SoC (5nm and below): floorplanning, placement, CTS, routing, extraction, physical verification, STA closure, timing/functional ECO, and automation of P&R flows using industry EDA tools.

Lead and execute backend digital physical design for SoC at 5nm and below: floorplanning, placement, CTS, routing, extraction, STA closure, ECOs, physical verification, and automation of EDA flows.

Lead and execute backend digital physical design for SoC at 5nm and below: floorplanning, placement, CTS, routing, extraction, physical verification, STA closure, timing/functional ECO, and automation of EDA flows using Cadence/Synopsys/Mentor toolchains.

Lead and execute backend digital physical design for SoC at 5nm and below, covering floorplanning, placement, CTS, routing, extraction, STA, ECOs, physical verification, and automation of EDA flows to achieve timing closure and right-first-time silicon.

Perform SOC physical design at block level including floorplanning, partitioning, placement, clock tree synthesis, routing and physical verification (LVS/DRC/ERC/Antenna). Execute STA, equivalence checks, crosstalk and noise analysis, power optimization, and implement timing/functional ECOs. Use formal verification and timing analysis to achieve congestion, timing and area metrics. Mentor team members and collaborate in a global, dynamic environment while adopting new tools and methodologies.

Lead and execute backend digital physical design for SoC at 5nm and below, including floorplanning, placement, CTS, routing, extraction, PV, STA closure, timing/functional ECO, and automation of EDA flows across Cadence/Synopsys/Mentor toolchains.

Lead and execute backend digital physical design for SoC at 5nm and below, including floorplanning, placement, CTS, routing, extraction, physical verification, STA closure, ECO implementation, and automation of EDA flows while collaborating across teams to improve turnaround time and quality.

Perform SOC physical design: floorplanning, partitioning, placement, CTS, routing, and physical verification (LVS/DRC/ERC/Antenna). Execute STA, equivalence checks, crosstalk and noise analysis, power optimization, timing/functional ECOs, and formal verification. Drive congestion resolution and timing closure, work independently and mentor team members in a global environment.

Lead hands-on design of digital and mixed-signal boards for energy storage products from architecture through mass production. Define converter topologies, oversee grounding, EMI/EMC, measurement, communications, protection, PCB layout, verification, and system characterization. Provide technical ownership, review designs and firmware, mentor engineers, solve lab and bring-up issues, and collaborate across multidisciplinary teams. Apply simulation tools, documentation, AI tools, and product lifecycle practices.

Designs digital and mixed-signal boards for energy storage products from concept through mass production. Responsibilities include analog measurement, communication interfaces, grounding, EMI/EMC, power distribution, protection circuits, PCB layout, simulation, verification, characterization, debugging, and design reviews. Collaborates across multidisciplinary teams and supports full-system validation.

Designs digital and mixed-signal boards for energy storage products from concept through mass production. Responsibilities include precision analog measurement, communication links, grounding, power distribution, EMI/EMC compliance, protection circuits, verification, characterization, debugging, and system bring-up. The role owns hardware subsystems, contributes to design reviews, mentors junior engineers, collaborates across disciplines, and documents designs throughout the product lifecycle.

Designs and owns analog IC blocks for PMICs and linear or switching DC-DC converters. Responsibilities include architecture development, transistor-level schematic design, simulation, verification, parasitic extraction, analog layout guidance, ESD and I/O ring design, silicon validation, debugging, and mentoring junior engineers. The role requires full ownership of multiple blocks and collaboration on subsystem and chip-top development.

Develops and maintains SystemVerilog and UVM verification environments for complex memory interface integrated circuits. Responsibilities include creating chip- and module-level testbench components, defining verification plans, executing coverage and assertions, debugging regressions, and supporting silicon analysis. The role collaborates closely with architects, designers, and verification engineers, with preferred knowledge of DDR4, DDR5, LPDDR5, and DIMM protocols.

Perform full-chip and chiplet-level static timing analysis (STA) from early design stages to signoff. Participate in top-level floorplanning and clock planning, integrate digital partitions and analog IP timing, optimize CAD signoff flows, and define timing/DFT constraints with logic and DFT teams to drive convergence.

Lead physical implementation of mixed-signal, low-power microcontroller SOCs from netlist to GDSII. Perform floorplanning, placement, CTS, timing closure, power integrity/IR drop and EM signoff, physical verification (DRC/LVS), metal-only ECOs, and collaborate with IP, CAD, synthesis, and DFT teams to ensure timely tapeout and first-pass silicon success.

Lead and perform custom analog and full‑custom digital layout at chip and block levels using Cadence Virtuoso; develop floorplans, power distribution, device‑matching, verify DRC/LVS/ERC, support tape‑out, mentor junior and offshore layout engineers, and standardize layout methodologies and processes.

Lead and manage VLSI design and verification teams for complex ASIC products. Own architecture, logic design, verification, simulation, physical layout coordination, program delivery, resourcing, vendor relationships, process improvement, and team development across multiple projects.

No role-specific responsibilities were provided. Based on the title, the Staff Analog Design Engineer would typically design and validate analog/mixed-signal circuits, collaborate with system and layout teams, support silicon bring-up and verification, and mentor junior engineers.

Design and simulate transistor-level analog/mixed-signal IC blocks (amplifiers, converters, power circuits), define architectures, integrate blocks into mixed-signal systems, present results to teams/customers, support layout, lab evaluation and test, mentor others, and improve design methodologies to meet power, timing and functional objectives.

Design and deliver high-quality memory layouts for advanced FinFET processes. Manage floor-planning, schedule, and chip integration; perform physical verification (LVS/DRC/ERC/Antenna/EM); lead and train layout teams; document methodologies and adapt to new process rules and automation.

The role involves architecting and maintaining the Verification Platform build system, developing tools and build flows, and educating teams on best practices.

Lead SoC execution from specification to silicon, define product and technology roadmaps, architect complex SoCs (NoC, memory, power, micro-architecture), select IP and foundry nodes, drive PPA optimization, govern silicon sign-off (synthesis, DFT, timing closure, tape-out), and coordinate cross-functional teams including design, verification, power, and silicon validation.

The UX/UI Engineer will design and develop AI-enhanced interfaces, conduct user research, and collaborate with teams to create scalable, accessible experiences for AI applications.

Lead design verification for complex ASICs: architect and build UVM/SystemVerilog DV environments, create constrained-random tests and coverage, run gate-level simulations and emulation, debug post-silicon bring-up, and manage ASIC bring-up activities across teams.

Design and qualify system power for Cisco networking products (10W–3000W+). Develop and execute power test plans, resolve field issues, engage vendors, review schematics/BOM/layout, and perform failure/root-cause analysis and corrective actions.