Top Design Engineer Jobs in Bangalore

Lead development of next-generation mixed-signal design automation flows, collaborate with analog IC teams to deploy AI-powered tools, mentor staff, and integrate external CAE tools with ADI internal capabilities.

Design and implement DFT features (scan chains, compression, BIST), perform DFT DRC and ATPG/MBIST, validate patterns in RTL/netlist, collaborate with verification and physical design, analyze test failures, mentor junior engineers.

Design and develop RTL for various digital components, work on micro-architecture, and collaborate with verification teams. Automate design tool flows as necessary.

Design and verify complex CPU/SoC IP by planning verification, building constrained-random UVM or C/C++ test environments, or using formal SVA tools. Debug RTL (Verilog) in simulation/emulation, write functional coverage, and close verification holes to meet tape-out requirements.

The Senior Engineer Design will manage engineering activities, including product design and continuous improvements, ensuring quality and on-time delivery while mentoring junior engineers.

Design and develop integrated circuits and ASICs across architecture, logic, verification and documentation. Drive system simulation, synthesis, place-and-route, timing and power analysis, and complex IC layout. Lead projects, mentor junior engineers, evaluate process flow and vendor capabilities, and champion product development from high-level design through tape-out.

Design and develop integrated circuits and ASICs, owning architecture, logic design, verification, and system simulation. Drive synthesis, place-and-route, timing and power analysis, and complex IC layout. Evaluate process flows and equipment, run experiments, review vendor capability, lead major projects, mentor junior engineers, and deliver new products/processes.

Design and develop integrated circuits and oversee ASIC development from architecture and logic design through system simulation, synthesis, place-and-route, timing and power analysis. Define module interfaces and layouts, evaluate process flow and equipment, run experiments, assess vendor capabilities, lead major projects, mentor junior engineers, and drive delivery of new products and processes.

Lead design and development of complex integrated circuits and ASICs, defining architecture, logic, simulation, synthesis, place-and-route, timing and power analysis. Oversee verification, documentation, experimental evaluation, vendor capability reviews, and mentor junior engineers while managing major projects from concept through delivery.

Lead verification strategy and architecture for complex digital and mixed-signal designs. Develop UVM-based environments, drive coverage closure, debug RTL and gate-level issues, mentor engineers, coordinate cross-functional verification sign-off, and lead post-silicon validation and customer interactions.

Lead pre-silicon verification for complex SoC/subsystem designs: define verification architecture and flows, implement UVM testbenches, drive coverage closure, apply formal and power-aware (UPF) verification, coordinate emulation/FPGA/firmware teams, verify NoC/interconnects and system-level use cases, and develop scalable DV methodologies to meet quality and schedule goals.

Lead DFT architect responsible for improving test architecture and coverage across SoC designs. Implement and run Tessent/Modus ATPG and MBIST flows, perform scan pattern simulation, diagnosis and post-silicon bring-up, and collaborate with test engineering for pattern delivery and debug.

The Design Verification Engineer performs functional verification of IP logic, develops verification plans, executes simulations, debugs issues, and maintains verification infrastructure.

Lead verification of Holoscan FPGA designs by defining and executing verification strategy. Build scalable constrained-random UVM/SystemVerilog environments, drive stimulus and coverage, collaborate with design and architecture teams, and incorporate AI-accelerated workflows to improve verification efficiency.

Lead physical implementation of high-frequency CPU core blocks from RTL to GDSII. Drive synthesis, place-and-route, timing closure, CTS, and signoff. Collaborate with architecture, RTL, and power teams for aggressive PPA optimization, improve physical design flows and automation, and solve core-specific datapath and congestion challenges.

The Design Verification Engineer will ensure functional correctness of IP blocks, develop test cases, enhance verification methods, and collaborate with teams for silicon success.

The Staff Design Verification Engineer leads verification strategies for complex designs, mentors junior engineers, collaborates across teams, and resolves verification challenges.

As a Staff Design Verification Engineer, lead the verification strategy for complex designs, mentor engineers, and ensure product quality through advanced methodologies.

Lead the development of verification strategies for mixed-signal designs, mentor junior engineers, and ensure product quality through sophisticated UVM-based environments.

The Senior Engineer will design and develop analog circuits, focusing on power delivery applications, and execute full-chip projects, contributing to product innovation.

Lead RTL design and micro-architecture of complex IPs/subsystems for MCU SoCs. Drive RTL quality (lint/CDC/RDC), support synthesis/simulation/STA, collaborate across teams for SoC integration, mentor juniors, and improve RTL methodologies.

Develop and maintain UVM/SystemVerilog and C/assembly simulation infrastructure for SoC-level verification. Create verification plans, random-constrained tests, assertions, coverage, and regressions for mixed-signal chips, and assist across specification, design, verification, DFT, and silicon debug.

Lead physical design for ASIC/SOC implementations. Conduct synthesis, analysis, verification, and optimization of designs. Manage team and improve design methodologies.

Seeking a Senior Engineer for digital RTL design in Timing and Communications. Responsibilities include developing RTL designs, optimizing for ASICs, and collaborating with analog teams on innovative solutions.

Develop and maintain CAD/EDA design automation flows, implement CI/CD pipelines, support EDA tool integration, and mentor teams on CAD flows.