Top Design Engineer Jobs in Bangalore

Design and qualify system power for Cisco networking products (10W–3000W+). Develop and execute power test plans, resolve field issues, engage vendors, review schematics/BOM/layout, and perform failure/root-cause analysis and corrective actions.

Design, develop, and verify ASIC blocks, clusters and top-level subsystems using UVM/SystemVerilog. Build and maintain DV infrastructure and testbenches, implement coverage, run gate-level simulations and emulation, support post-silicon bring-up, and lead ASIC bring-up activities with cross-functional teams.

Lead technical assessor reviewing power-electronics designs through development to production. Analyze converter topologies, simulations, thermal, EMI/EMC, magnetic components, PCB layouts, and embedded interfaces. Produce design review reports, present findings, drive technical discussions, and support reliability/root-cause investigations.

Lead technical architect for embedded electronic hardware for brake and transit applications. Own hardware development from concept through validation and production, drive schematic/PCB design reviews, verification and EMC/environmental testing, lead debugging and root-cause analysis, mentor engineers, collaborate with systems, software, suppliers, manufacturing, and ensure safety-compliant, manufacturable products.

You will own parts of IP design verification, develop test plans and UVM components, and manage verification strategies and coverage closure.

As a Design Verification Engineer, you will ensure the quality of advanced RADAR products, involving verification of IP, Subsystem, and SoC designs, collaborating with cross-functional teams, and developing robust verification methodologies.

The Design Verification Engineer will develop test plans, create verification environments, and evaluate hardware designs using various methodologies focused on automotive connectivity solutions.

This role involves driving verification strategies for SoC designs, developing Test Plans, and collaborating with teams for verification goals in digital design and protocols.

Design and execute verification strategies and reusable SystemVerilog/UVM testbenches. Implement tests, manage regressions, collect coverage, debug across simulation, emulation, and silicon bring-up, and collaborate with architects, RTL, physical design, firmware, and software teams to ensure silicon-quality designs.

This role involves designing District Cooling Systems using CAD/BIM software, preparing bid submissions, developing tender specifications, and liaising with teams and government agencies for project collaboration.

Verify ASIC memory subsystem designs for GPUs/SOCs using advanced methodologies (SV/UVM). Define verification scope, develop infrastructure, create test plans, build BFMs/monitors/checkers/scoreboards, run coverage-driven verification, and collaborate with architects, designers, and silicon teams.

Lead IP/subsystem roadmap and architecture, design complex IPs for edge and automotive (ASIL-D), drive development from concept to silicon-quality IP, ensure quality/process improvements, mentor global teams, and collaborate across SoC/system functions.

Lead architecture and micro-architecture for ASICs, ensuring high-quality digital design; collaborate with teams for robust delivery and mentor engineers.

The Senior Engineer I will design System-on-Chip solutions for wireless applications, collaborate across teams, and support silicon IC qualifications.

Lead subsystem/block physical design closure focusing on timing, congestion, power integrity, and implementation. Collaborate with SoC teams on clocking and floorplanning, implement UPF and low-power techniques, develop closure methodologies and automation, mentor engineers, and work cross-functionally with RTL, STA, power, verification, and backend teams to identify and mitigate physical design risks.

The Sr. Staff Engineer will design and validate high-performance analog and mixed-signal IP blocks, lead cross-functional teams, and mentor junior engineers.

Lead end-to-end RTL-to-GDSII execution for SoC programs, ensuring successful tapeouts, signoff, and collaboration across teams while championing automation and low-power design strategies.

The Staff Engineer will lead digital design engineering efforts, mentor junior engineers, and develop specifications and RTL design while also collaborating with verification teams and supporting post-silicon activities.

Verify ASIC design, architecture and micro-architecture of memory subsystem IPs. Define verification scope, develop test plans, infrastructure, BFMs, monitors, checkers and scoreboards. Use coverage-driven methodologies (SystemVerilog/UVM/VMM), assertions, random stimulus, and functional coverage. Collaborate with architects, designers and pre/post-silicon teams to achieve verification closure.

Lead and own complex analog IP and smaller ICs (PMICs, DC-DC, LDOs), design and compensate control loops, define block-level specs and error budgets, drive analog layout and extraction, validate silicon, mentor engineers, and manage a small team through full IC development to production while ensuring quality and schedule adherence.

The role involves implementation of NoC and Uncore systems, focusing on PPA optimization. Key responsibilities include leading physical design, driving co-design across levels, and mentoring junior engineers.

Responsible for software development related to IP blocks, defining HW/SW interfaces, collaborating with HW engineers, and ensuring efficient programmability and usability for software consumption. Involves pre-silicon validation and development of drivers and firmware prototypes.

Lead and mentor digital IP design teams to architect, implement, and deliver configurable RTL IPs. Drive IP cataloging, third-party IP evaluation, PPA and verification best practices, interface integration (DDR, PCIe, MIPI, etc.), DFT/CDC/formal flows, synthesis/STA, and cross-team alignment to accelerate SoC development.

The Staff Design Verification Engineer will lead verification strategies, mentor engineers, and solve complex verification challenges for mixed-signal designs at Analog Devices.

Lead design and development of analog and mixed-signal IP (amplifiers, comparators, data converters, references, monitors). Perform transistor-level schematic design, simulation, PVT and Monte Carlo analysis, collaborate with layout and SoC teams, support silicon bring-up and validation, and mentor junior engineers.