Top Design Engineer Jobs in Bangalore

Lead verification for complex CPU/SoC IP and subsystems: define verification strategies and test plans, build verification environments, run and debug simulations/emulations, apply random-stimulus and coverage-driven techniques, and mentor engineers while improving verification methodologies and tools.

Design and develop rail track alignment and related civil engineering deliverables for infrastructure projects. Produce technical drawings, calculations, and specifications; coordinate with multidisciplinary teams and clients; ensure compliance with engineering standards and support project delivery.

Design and execute offsite-built modular pump packages and plant rooms for HVAC and fire pump applications. Develop 3D models, 2D drawings, BOMs, fabrication docs, and provide technical support through project delivery, manufacturing coordination, site surveys, and commissioning while ensuring standards, quality, and design-for-manufacture practices.

Design and engineer low-voltage electrical control panels (MCC, PLC, VFD, HVAC, pump panels). Produce schematics, GA drawings, wiring diagrams, BOMs; perform load and cable calculations; select components; support manufacturing, FAT/SAT, commissioning, and documentation; coordinate with projects, procurement, and customers.

Lead the design and development of mechanical components for aerospace power products, ensuring adherence to engineering principles and standards. Manage projects, support engineering teams, and maintain documentation.

As a Senior ASIC Design Verification Engineer, you will validate ASIC features using UVM, develop verification environments, and collaborate with teams for debugging and validation.

Design and implement high-performance ASIC/SoC RTL, drive architecture and implementation decisions, perform timing/power optimization, validate silicon through debug, emulation and system bring-up, and document/improve design and flow methodologies.

Design and implement RTL for ASIC/FPGA front-end flow from specification to RTL/Netlist. Micro-architect and code RTL, perform lint and CDC checks, support sustenance designs, and collaborate with hardware/board engineers for system-level and board validation using company hardware design tools.

Develop and maintain a Verification Platform for Design Verification. Collaborate with engineers to create reusable testbench components and educate teams on best practices.

Develop and maintain the Verification Platform, collaborate with engineers to create reusable testbench components, and educate teams on best practices.

Design and develop analog/RF signal chains for automotive battery management systems. Responsibilities include circuit design, simulations, and post-silicon validation.

The Principal Engineer will define architecture and specifications for complex SoCs, collaborate with teams, review designs, and mentor junior members.

The NVM IP Platform Lead will oversee the NVM IP onboarding, release, and support processes, manage a diverse NVM IP portfolio, and mentor junior engineers.

Lead IP design blocks for PMICs and power management ICs. Design and optimize analog blocks (charge pumps, LDOs, oscillators, SAR ADCs, bandgaps, protection), perform control-loop compensation, guide analog/FET layout and parasitic-aware simulation flows, resolve technical risks, set design methodologies, and collaborate cross-functionally to drive silicon success. Individual contributor role focused on product development.

The Physical Design Engineer will manage the physical design flow, perform timing analysis, and conduct physical verification, while collaborating with teams and interfacing with stakeholders to ensure project delivery.

The Senior Design Verification Engineer will develop verification plans, design digital blocks, support DFT implementation, mentor junior engineers, and engage in IP-level verification tasks while ensuring spec compliance and documentation quality.

Define verification plans, lead sub-team activities, develop SystemVerilog/UVM environments, debug RTL errors, and support junior engineers.

Lead verification of digital blocks in mixed-signal SoCs: design testbench architecture and testplans, develop UVM/constrained-random environments, close functional and code coverage, debug and integrate block-level testbenches at SoC level, support post-silicon bring-up and ATE pattern development, and apply ML techniques to accelerate verification.

Perform full-chip and chiplet-level static timing analysis (STA) from early design stages to signoff. Participate in top-level floorplanning and clock planning, integrate digital partitions and analog IP timing, optimize CAD signoff flows, and define timing/DFT constraints with logic and DFT teams to drive convergence.

Lead physical implementation of mixed-signal, low-power microcontroller SOCs from netlist to GDSII. Perform floorplanning, placement, CTS, timing closure, power integrity/IR drop and EM signoff, physical verification (DRC/LVS), metal-only ECOs, and collaborate with IP, CAD, synthesis, and DFT teams to ensure timely tapeout and first-pass silicon success.

Lead verification for complex SoC power-management designs: define verification plans and coverage, architect and implement UVM-based testbenches, run block-to-chip verification and gate-level simulations, integrate VIPs, debug failures, drive coverage closure, mentor engineers, and support ATE vector bring-up.

Lead and own end-to-end subsystem design verification: define DV processes, architect and implement UVM/C testbenches, develop and execute test plans, collaborate across IP/SoC teams, debug simulation failures, drive coverage closure and support post-silicon bring-up.

Lead block-level chip planning and perform custom analog and full-custom digital layout for CMOS/BiCMOS circuits. Develop floorplans, power distribution, shielding, and device-matching layouts; execute schematic-driven layouts, verify DRC/LVS/ERC, support chip integration and tape-out, mentor junior/offshore engineers, and improve layout processes and workflows.

Lead and perform custom analog and full‑custom digital layout at chip and block levels using Cadence Virtuoso; develop floorplans, power distribution, device‑matching, verify DRC/LVS/ERC, support tape‑out, mentor junior and offshore layout engineers, and standardize layout methodologies and processes.

Lead and manage VLSI design and verification teams for complex ASIC products. Own architecture, logic design, verification, simulation, physical layout coordination, program delivery, resourcing, vendor relationships, process improvement, and team development across multiple projects.