Role Overview
As an Integrated Voltage Regulator (IVR) Design Engineer, you will be responsible for the architecture, design, and implementation of high-performance power management solutions directly integrated onto advanced processors (CPUs, GPUs, or SoCs). You will work at the intersection of Analog/Mixed-Signal IC design and Power Electronics to improve energy efficiency and performance in next-generation computing systems.
Key Responsibilities
Circuit Architecture and Design: Develop and refine analog topologies such as Operational Amplifiers (Op-Amps), Bandgap References, Data Converters (ADC/DAC), and Phase-Locked Loops (PLLs).
Design and Simulation: Perform transistor-level design using industry-standard tools (like Cadence Virtuoso). Conduct extensive Monte Carlo simulations, corner analysis, and noise analysis to ensure high yield and reliability.
Layout Oversight: Collaborate closely with layout engineers to guide critical placement and routing, focusing on matching, shielding, and minimizing parasitic capacitance/resistance.
Verification: Use SPICE-based simulators to verify circuit functionality against rigorous performance specifications (speed, power, gain, etc.).
Post-Silicon Characterization: Bench-test silicon prototypes in the lab to validate performance against pre-silicon models and debug hardware anomalies
Required Technical Skills
Transistor Fundamentals: Expert knowledge of MOSFET/BJT device physics, small-signal modeling, and aging effects.
EDA Tool Proficiency: Mastery of Cadence (Spectre/Virtuoso), Mentor Graphics, or Synopsys tool suites.
Signal Integrity: Deep understanding of thermal noise, jitter, crosstalk, and power supply rejection ratio (PSRR).
Mixed-Signal Flow: Familiarity with Verilog-A or Verilog-AMS for behavioral modeling of analog blocks.
Qualifications
Education: BS, MS, or PhD in Electrical Engineering (EE) with a concentration in Analog IC Design.
Experience: 3 - 7 years of experience in analog design (FinFET or planar CMOS nodes).
Analytical Mindset: Strong mathematical background for analyzing feedback systems and stability.
Job Type:Experienced HireShift:Shift 1 (India)Primary Location: India, BangaloreAdditional Locations:Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.Skills Required
- BS, MS, or PhD in Electrical Engineering with a concentration in Analog IC Design
- 3–7 years of experience in analog design
- Experience with FinFET or planar CMOS nodes
- Expert knowledge of MOSFET and BJT device physics, small-signal modeling, and aging effects
- Mastery of Cadence Spectre/Virtuoso, Mentor Graphics, or Synopsys tool suites
- Deep understanding of thermal noise, jitter, crosstalk, and power supply rejection ratio
- Familiarity with Verilog-A or Verilog-AMS for behavioral modeling
- Strong mathematical background for feedback-system and stability analysis
Intel Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Intel and has not been reviewed or approved by Intel.
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Leave & Time Off Breadth — Sabbaticals and paid time off are highlighted as signature elements, with an established program offering four weeks after four years or eight weeks after seven years. This distinctive time off is positioned as a meaningful part of the overall package.
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Parental & Family Support — Paid bonding leave of 12 weeks and a New Parent Reintegration program, plus fertility benefits around $40,000 and up to $15,000 adoption reimbursement with no lifetime cap, are clearly stated. These programs are presented as standout components alongside broader family support resources.
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Healthcare Strength — Multiple medical plan options with 2026 updates, a shift to Spring Health for EAP, and in‑network virtual medical visits covered at 100% beginning in 2026 indicate a comprehensive offering. These features signal an emphasis on robust medical access and mental health support.
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