Top Design Engineer Jobs in Bangalore

Lead and own complex analog IP and smaller ICs (PMICs, DC-DC, LDOs), design and compensate control loops, define block-level specs and error budgets, drive analog layout and extraction, validate silicon, mentor engineers, and manage a small team through full IC development to production while ensuring quality and schedule adherence.

The role involves implementation of NoC and Uncore systems, focusing on PPA optimization. Key responsibilities include leading physical design, driving co-design across levels, and mentoring junior engineers.

Responsible for software development related to IP blocks, defining HW/SW interfaces, collaborating with HW engineers, and ensuring efficient programmability and usability for software consumption. Involves pre-silicon validation and development of drivers and firmware prototypes.

Lead and mentor digital IP design teams to architect, implement, and deliver configurable RTL IPs. Drive IP cataloging, third-party IP evaluation, PPA and verification best practices, interface integration (DDR, PCIe, MIPI, etc.), DFT/CDC/formal flows, synthesis/STA, and cross-team alignment to accelerate SoC development.

The Staff Design Verification Engineer will lead verification strategies, mentor engineers, and solve complex verification challenges for mixed-signal designs at Analog Devices.

The Principal IO Mixed Signal Design Engineer will integrate and verify mixed signal blocks in high-speed IOs for FPGAs, develop custom circuits, and support post-tapeout phases.

Provide technical consultation and support for Cadence's digital & sign-off tools to customers, assisting in design implementation and problem-solving. Mentor a team and author knowledge content while driving product improvements based on customer feedback.

Drive physical implementation and timing closure for high-performance chip designs. Architect advanced clock distribution and global interconnects, optimize RC/jitter/IR issues, collaborate with RTL/architecture teams, mentor engineers, and sign off on implementation using industry EDA tools.

Lead end-to-end physical design (synthesis, floorplan, P&R, signoff) for complex IPs, co-optimize RTL and microarchitecture to meet aggressive PPA targets, solve timing/routing/IR issues, apply advanced techniques across product classes, and mentor junior engineers.

Provide customer-facing technical leadership for Ethernet FPGA IP: lead design bring-up and validation across 10G–800G, debug and optimize performance, validate protocol compliance (AN/LT, IEEE1588 PTP), produce reference designs and documentation, and collaborate with design, validation, product engineering, and sales to resolve issues and improve IP quality.

The Staff Design Verification Engineer will lead verification strategies for complex designs, mentor junior engineers, and resolve verification challenges while representing the company to customers and partners.

Define and lead verification strategy and plans, develop SystemVerilog/UVM environments for blocks and SoCs, coordinate verification activities, debug RTL functional issues, and improve verification methodology.

Lead verification strategy and plans for mixed-signal IP and SoC blocks. Develop SystemVerilog/UVM environments, coordinate verification activities, debug RTL functional issues, collect coverage, manage regressions, and improve verification methodology.

Lead verification strategy and plans for blocks and SoCs; develop SystemVerilog/UVM environments; coordinate and lead verification activities; debug RTL functional issues; improve verification methodology and manage coverage and regressions.

Lead and define verification strategies and plans for digital/SoC blocks, develop SystemVerilog/UVM environments, debug RTL functional issues, coordinate verification activities, and improve verification methodology.

Develop and execute functional verification plans and testbenches for FPGA designs using SystemVerilog and UVM/OVM. Create verification environments, run simulations (including gate-level and power/timing-aware), root-cause and debug pre-silicon issues, collaborate with architects and RTL/physical design teams, and document verification strategy and results.

Lead SoC execution from specification to silicon: define SoC architecture and product strategy, select IP and foundry nodes, drive PPA optimization, govern silicon sign-off, and coordinate cross-functional teams (design, verification, DFT, PD, power, SiVal) to deliver first-time-right silicon.

Lead product engineer responsible for product development, verification expertise in memory protocols, driving product adoption, and collaborating across teams to meet customer needs.

Develop and execute verification plans and UVM-based testbenches to validate RISC-V CPU microarchitecture. Perform functional coverage analysis, system-level simulations, debugging, automation with scripting, and collaborate with architects and RTL designers to close verification gaps and improve verification infrastructure.

The Senior Engineer Design will manage engineering activities, including product design and continuous improvements, ensuring quality and on-time delivery while mentoring junior engineers.

Design and develop integrated circuits and ASICs, owning architecture, logic design, verification, and system simulation. Drive synthesis, place-and-route, timing and power analysis, and complex IC layout. Evaluate process flows and equipment, run experiments, review vendor capability, lead major projects, mentor junior engineers, and deliver new products/processes.

Lead design and development of complex integrated circuits and ASICs, defining architecture, logic, simulation, synthesis, place-and-route, timing and power analysis. Oversee verification, documentation, experimental evaluation, vendor capability reviews, and mentor junior engineers while managing major projects from concept through delivery.