Top Python Jobs in Bangalore

Lead AWS cost and performance optimization for ThousandEyes cloud platform: drive FinOps practices, identify savings, improve resource utilization and autoscaling, build automation and dashboards, support cost governance and stakeholder reporting, mentor engineers, and balance reliability, scalability, performance, and cost across large-scale cloud systems.

Build and improve software for SambaRack, a rack-scale AI infrastructure platform. Responsibilities include developing hardware management, monitoring, control, diagnostics, telemetry, observability, and infrastructure services; improving performance, reliability, and scalability; integrating software with hardware; resolving bottlenecks; and collaborating with hardware, DevOps, QA, and product teams. The role supports production, enterprise, customer-managed, and air-gapped deployments.

Design and build reliable software for SambaRack, a rack-scale AI infrastructure platform. Responsibilities include hardware control, monitoring, diagnostics, telemetry, observability, distributed systems, and hardware-software integration. The role improves system performance, scalability, and reliability; leads technical architecture; resolves systemic risks; collaborates across engineering teams; and mentors engineers supporting enterprise and air-gapped deployments.

Define and own the end-to-end architecture of SambaStack, an enterprise AI inference platform. Set technical strategy and standards across engineering teams, lead design reviews, resolve scalability and reliability risks, and guide platform evolution. Partner with ML, product, QA, and DevOps teams to make architectural decisions, evaluate emerging technologies, mentor engineers, and design systems for production-scale AI inference workloads.

Design and own the architecture of SambaRack’s infrastructure and management platform for rack-scale AI systems. Lead hardware-software integration, control, monitoring, diagnostics, observability, reliability, and scalability efforts. Establish architectural standards, guide technical direction, resolve systemic risks, and collaborate with Hardware Engineering, DevOps, QA, and Product teams. Mentor engineers and evaluate technologies for enterprise, production, customer-managed, and air-gapped deployments.

Validates customer-focused Service Provider and Cloud networking solutions through system-level testing, automation, troubleshooting, and solution certification. Designs and executes test plans, builds representative lab environments, configures Junos/EVO networking devices, develops Python or Robot Framework automation, performs performance and scale testing, analyzes results, conducts root cause analysis, and collaborates with customers, field engineers, and development teams. Produces technical reports and presentations while improving testing methodologies and leveraging AI-powered testing tools.

Leads the architecture and implementation of AIOps automation across cloud AI platforms. Builds self-healing infrastructure, RAG knowledge tools, conversational support bots, observability pipelines, predictive anomaly detection, and operational dashboards. Eliminates support toil, improves MTTR and ticket deflection, standardizes logs and telemetry, and mentors L1/L2 engineers. Requires strong AWS or GCP, Kubernetes, infrastructure-as-code, scripting, observability, and generative AI production experience.

Leads system test engineering for on-premises and cloud Network Admission Control and identity products. Architects scalable Python-based automation and AI-driven test frameworks, designs automated testing environments, diagnoses complex network integration issues, and defines testing strategies for REST APIs, performance, and system reliability. Provides technical leadership, mentors engineers, drives root-cause analysis, and guides cross-functional execution across networking, security infrastructure, and cloud-native technologies.

Verify next-generation PCI Express controller ASICs at IP and subsystem levels. Develop reusable bus functional models, monitors, checkers, scoreboards, test plans, tests, and coverage-driven constrained-random verification environments using UVM and related methodologies. Collaborate with architects, designers, and pre- and post-silicon verification teams to ensure design correctness.

Verify PCI Express controller ASIC designs at IP and subsystem levels using UVM and coverage-driven methodologies. Develop reusable bus functional models, monitors, checkers, scoreboards, test plans, tests, and verification infrastructure. Collaborate with architects, designers, and pre- and post-silicon verification teams to validate design correctness. The role requires experience with Verilog, SystemVerilog, constrained-random verification, functional coverage, PCIe or related interconnect protocols, and industry-standard simulation and debug tools.

Owns CI/CD, cloud infrastructure, DevSecOps, FinOps, and reliability across Azure and AWS. Builds Azure DevOps and GitHub Actions pipelines, provisions infrastructure with Bicep and Terraform, manages Docker and Kubernetes workloads, supports AWS-to-Azure migration, and administers monitoring, security, Linux systems, and cloud costs. Automates operational tasks using Python, Bash, or PowerShell while coordinating workload cutovers and governance activities.

Develop compact SPICE models for LDMOS, CMOS, BJT, diode, resistor, and capacitor devices. Characterize inter-device parasitics and bipolar action, perform electrical and multiphysics modeling, and develop long-term MOS/LDMOS degradation models. The role requires strong device physics, hands-on electrical measurements, Python programming, and familiarity with SPICE-like circuit simulators.

Design, develop, and support enterprise data platforms, ETL/ELT pipelines, Oracle and SQL/PLSQL solutions, data warehouses, and risk and regulatory reporting systems. Provide production support, troubleshoot batch and data issues, optimize performance, automate validation and reconciliation, and ensure data quality, governance, lineage, and audit readiness. Collaborate with Risk, Finance, Regulatory, Business, and Technology stakeholders while providing technical leadership and mentoring.

Develop and execute ASIC verification plans, build SystemVerilog OVM/UVM testbenches, implement reusable VIP, and achieve code and functional coverage closure. Apply constraint-random verification, assertions, object-oriented programming, and ASIC verification methodologies. Collaborate with internal teams, external customers, and VIP providers while addressing complex semiconductor design challenges. Low-power UPF and formal verification experience are advantageous.

Leads digital architecture, RTL design, low-power design, synthesis, timing analysis, and tool-flow execution for power-management ICs. Drives designs from architecture through RTL, verification, implementation, system-level bring-up, and post-silicon validation. Collaborates with analog, digital, verification, architecture, and project-management teams globally while improving design processes, reuse, and quality. Applies expertise in ASIC and mixed-signal development, digital control peripherals, power-converter architectures, and power-performance-area trade-offs.

Lead digital design architecture and end-to-end IP or SoC development for power management products. Own RTL implementation, low-power design, synthesis, timing analysis, physical-design interfaces, and front-end tool-flow deployment using RTL2GDS methodologies. Collaborate with analog, digital verification, architecture, project management, and global engineering teams. The role requires leadership in complex ASIC and mixed-signal chip development, platform-based design, microprocessor interconnect integration, and successful IC product releases.

Leads digital architecture, RTL design, low-power implementation, synthesis, timing analysis, and verification support for power management ASICs and mixed-signal ICs. Drives designs from architecture through RTL, pre-silicon bring-up, implementation, and post-silicon validation. Collaborates with analog, digital verification, architects, and project teams across global locations while improving design tools, flows, reuse, and quality processes.

Leads digital architecture, RTL implementation, low-power design, synthesis, timing analysis, and verification flows for power management ICs. Collaborates globally with analog, digital, verification, and project teams; supports pre-silicon platforms, post-silicon validation, IP quality control, and system-level feature bring-up. The role requires expertise in ASIC and mixed-signal development, power converter architectures, digital control peripherals, and power-performance-area trade-offs.

Own analog mixed-signal verification for power management products, including defining and executing verification plans, behavioral modeling, simulations, testbench development, coverage, debugging, and system integration. Develop and improve AMS design verification methodologies, coding processes, and integration flows. Collaborate with design and cross-functional teams while verifying power management blocks using Verilog-AMS, Verilog-A, SystemVerilog, SVA, and scripting languages.

Develop and validate PDK collateral for advanced semiconductor process nodes, including parasitic extraction, physical verification, LVS, runsets, device modeling, and design-rule validation. Build test structures, automate QA workflows, debug issues, collaborate with EDA vendors and cross-functional teams, and document design flows and methodologies for silicon designers.

Develop, validate, debug, optimize, and support DRC runsets and physical verification rule decks for advanced semiconductor process nodes. Translate design rules into geometric, connectivity, density, and process-specific checks using Calibre, ICV, and Pegasus. Create validation and regression suites, automate development and deployment workflows, improve runtime and scalability, resolve production issues, and collaborate with process, CAD, EDA, and design teams. Guide team members and apply AI-based automation to improve productivity.

Develop, validate, debug, and optimize DRC runsets and rule decks for advanced semiconductor process nodes. Translate design rules into production-quality physical verification checks, create validation and regression suites, improve runtime and scalability, and support production users. Collaborate with process development, CAD/EDA, design rule owners, and design teams. Use physical verification tools, scripting, automation, and AI-based techniques to resolve complex design rule implementation challenges.

Develop and maintain small- to mid-scale backend applications, including design, development, testing, deployment, debugging, database schema design, and query optimization. Candidates should understand data structures, algorithms, time and space complexity, normalized database design, unit and integration testing, and communicate clearly. Experience with Python or Go, Kafka, AWS, relational databases, and NoSQL systems is beneficial.

Leads ServiceNow engineering and operations with a focus on ITSM, platform architecture, integrations, upgrades, governance, security, and performance. Manages and mentors ServiceNow engineers, serves as a technical escalation point, translates client requirements into solutions, and oversees project roadmaps and release cycles. The role also establishes development and deployment best practices while partnering with stakeholders to drive platform reliability and continuous improvement.

Build and scale full-stack distributed applications for Meraki Dashboard and Cisco Catalyst networking products. Own features from design through production deployment, improve reliability and performance through testing and monitoring, and solve complex software and networking issues. Provide technical leadership by mentoring engineers, influencing architecture, leading complex projects, and collaborating with engineering, product, and globally distributed teams.