Top Python Jobs in Bangalore

The Staff Design Verification Engineer leads verification strategy for complex analog and mixed-signal designs, developing environments and mentoring engineers while ensuring product quality.

Design, develop and maintain cloud-native monitoring and network hygiene solutions and analytics dashboards. Build microservices, REST APIs, and data flows; ensure security, reliability, documentation, and tests; mentor engineers and run agile teams; perform code reviews and integrate third-party systems.

Lead architecture and implementation of advanced DFT strategies (scan, JTAG, MBIST/LBIST), oversee ATPG and test compression, perform pre/post-silicon verification and debug, improve test coverage and collaborate with RTL and physical teams for timing and silicon bring-up.

As a Principal Software Engineer, you will design and develop secure web applications and distributed systems, leveraging AI/ML for data processing. This role involves leading architecture, ensuring performance and security, and mentoring engineers while integrating real-time analytics and intelligent data workflows.

The Senior Python Developer will build scalable services, design server architecture, mentor junior engineers, and enhance automation processes.

Lead architecture and reliability for a high-scale alerting pipeline: evaluate rule- and ML-based detections, ensure end-to-end delivery and idempotency, correlate diverse telemetry into topologies for LLM-driven reasoning, mentor engineers, and drive org-level technical decisions.

Develops, debugs, and integrates embedded product software for vehicle systems. Owns diagnosis, AUTOSAR BSW integration, diagnostic configuration, and verification activities; mentors junior engineers and leads smaller projects while collaborating across cross-functional teams to deliver verified software builds.

Design, develop, and maintain cloud-hosted SaaS web applications for insurance/reinsurance. Build responsive front ends with Angular/TypeScript, develop RESTful APIs in Python/FastAPI, support databases (SQL/NoSQL), create UI automation tests, troubleshoot issues, and incorporate AI to accelerate development and deliver AI-driven features.

Define and lead verification strategy and plans, develop SystemVerilog/UVM environments for blocks and SoCs, coordinate verification activities, debug RTL functional issues, and improve verification methodology.

Lead verification strategy and plans for mixed-signal IP and SoC blocks. Develop SystemVerilog/UVM environments, coordinate verification activities, debug RTL functional issues, collect coverage, manage regressions, and improve verification methodology.

Lead verification strategy and plans for blocks and SoCs; develop SystemVerilog/UVM environments; coordinate and lead verification activities; debug RTL functional issues; improve verification methodology and manage coverage and regressions.

Lead and define verification strategies and plans for digital/SoC blocks, develop SystemVerilog/UVM environments, debug RTL functional issues, coordinate verification activities, and improve verification methodology.

Own release readiness and delivery of SiFive IP customer drops; manage integration/configuration issues across Core/UnCore; generate release collateral and perform quality checks; drive schedule and risk tracking; collaborate with sales/support; debug cross-functionally and improve release automation.

Perform functional verification of FPGA designs by developing verification plans, testbenches, and environments (UVM/OVM). Run simulations, analyze power and timing, debug pre-silicon issues, and collaborate with architects, RTL and physical design teams. Maintain verification infrastructure, execute gate-level and power-aware strategies, and document verification results and reviews.

Develop and execute functional verification plans and testbenches for FPGA designs using SystemVerilog and UVM/OVM. Create verification environments, run simulations (including gate-level and power/timing-aware), root-cause and debug pre-silicon issues, collaborate with architects and RTL/physical design teams, and document verification strategy and results.

Operate and evolve high-performance data capture pipelines for capital markets: provision and tune Linux servers, automate deployments with Ansible, manage containerized production workloads, support data copying/scheduling, perform networking troubleshooting, and execute risk-aware OS and application updates while working US Eastern hours and occasional weekends.

Design and own micro-architecture and RTL for memory sub-system modules. Collaborate with architects, verification, timing, VLSI, FPGA and software teams to implement, verify, prototype, synthesize, timing-clean, and debug designs through post-silicon bring-up.

Develop and improve GPU profiling libraries and Nsight tools, design metrics and data-collection methodologies, read HW specs to design solutions, write unit tests and support multiple platforms from supercomputers to embedded systems.

Design, develop, and execute test plans for SONiC and Junos on Broadcom-based switches. Validate L2/L3 features, SAI integration, ASIC behavior, optical modules, and telemetry. Automate tests using Python and Robot Framework, perform deep debugging across ASIC/NOS/control/data planes, and contribute to SONiC open-source improvements.

Designs and executes automated and manual tests for software, firmware, and UI/REST APIs. Writes test plans and scripts, debugs issues, collaborates with internal and outsourced teams, and helps maintain quality standards and automation tools.

Define and optimize DFT architecture (scan, compression, MBIST, JTAG), implement SCAN/MBIST insertion and ATPG flows, support post-silicon bring-up and failure analysis, collaborate with physical design and product/test teams, and mentor new team members on DFT methodology and flows.

Lead an 8-10 engineer team owning courier systems (dispatch, matching, pricing, ETA). Set technical direction, drive data-driven decisions and experiments, partner with data science, ensure reliability and scalability of low-latency distributed systems, and own hiring, performance, and operational excellence.

Lead architecture and implementation of scalable observability and FinOps platforms. Design self-service frameworks, define and enforce SLOs/SLIs, manage high-cardinality telemetry and tracing, optimize cloud cost metrics, mentor engineers, collaborate with Finance and leadership, and resolve performance and cost issues across distributed systems.

Lead architecture and development of cloud-native, containerized microservices. Build event-driven backends, gRPC/REST APIs, and telemetry pipelines using graph and time-series databases. Integrate AI/ML models into data pipelines and deploy applications with Docker and Kubernetes.

Develop and maintain high-performance, scalable risk metrics engines and workflows. Write production-grade backend code, implement cloud-first architectures (AWS), integrate AI-enabled tools, follow CI/CD and testing best practices, and collaborate with quantitative engineers and product managers to support firm-wide risk, liquidity, and trading analytics.