We are looking for a skilled DRC Runset Engineer to develop, validate, support, and optimize Design Rule Checking runsets for advanced semiconductor process technology nodes. The candidate will work closely with process development teams, design rule owners, CAD/EDA teams, and design groups to translate design rules into robust, efficient, and production-quality rule decks.
The role requires strong expertise in DRC rule deck development using industry-standard physical verification tools such as Siemens Calibre, Synopsys ICV, and Cadence Pegasus, along with strong debugging, automation, and problem-solving skills.
Key Responsibilities:
• Develop, maintain, and support DRC runsets/rule decks for advanced semiconductor process nodes.
• Translate process design rules into accurate and efficient physical verification checks.
• Develop and validate complex geometric, connectivity, density, and process-specific design rule checks using tools such as Calibre, ICV, and Pegasus.
• Create comprehensive test cases to validate rule deck functionality, coverage, and correctness.
• Debug DRC rule deck issues and resolve customer/user-reported problems.
• Improve runset quality, runtime efficiency, scalability, and usability.
• Work closely with process developers, design rule owners, CAD teams, and design teams to collect, understand, and refine requirements.
• Automate rule deck development, validation, regression, and deployment processes to improve efficiency and quality.
• Design and implement unit-level and end-to-end validation methodologies for DRC runsets and physical verification flows.
• Provide solutions for complex physical verification and design rule implementation challenges.
• Guide team members on technical issues, debugging strategies, and best practices.
• Use AI-based tools and automation techniques to improve rule deck development, validation, and debug productivity.
• Support production users and resolve runset-related issues in a timely manner.
• Work in a fast-paced, dynamic environment with strong ownership, creativity, and attention to quality.
Job Type:Experienced HireShift:Shift 1 (India)Primary Location: India, BangaloreAdditional Locations:Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A
Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.Skills Required
- 10+ years of experience with a bachelor's degree, or 8+ years with a master's degree, in Electronics, VLSI, Computer Engineering, or a related field
- Strong experience in DRC rule deck or runset development for semiconductor technologies
- Hands-on expertise with one or more physical verification tools: Siemens Calibre, Synopsys ICV, or Cadence Pegasus
- Understanding of semiconductor manufacturing processes, layout design rules, and physical verification concepts
- Experience writing, debugging, and optimizing DRC checks
- Hands-on experience with Cadence Virtuoso, Calibre DRV, or IC WorkBench
- Strong programming or scripting skills in Python, Perl, Tcl, or Shell scripting
- Ability to create and maintain validation test cases and regression suites
- Strong debugging, analytical, and problem-solving skills
- Ability to collaborate cross-functionally and communicate effectively with technical stakeholders
- Experience automating runset development, validation, and release processes
Intel Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Intel and has not been reviewed or approved by Intel.
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Leave & Time Off Breadth — Sabbaticals and paid time off are highlighted as signature elements, with an established program offering four weeks after four years or eight weeks after seven years. This distinctive time off is positioned as a meaningful part of the overall package.
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Parental & Family Support — Paid bonding leave of 12 weeks and a New Parent Reintegration program, plus fertility benefits around $40,000 and up to $15,000 adoption reimbursement with no lifetime cap, are clearly stated. These programs are presented as standout components alongside broader family support resources.
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Healthcare Strength — Multiple medical plan options with 2026 updates, a shift to Spring Health for EAP, and in‑network virtual medical visits covered at 100% beginning in 2026 indicate a comprehensive offering. These features signal an emphasis on robust medical access and mental health support.
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