Top Python Jobs in Bangalore

The role involves leveraging experience and knowledge to provide strategic value and contribute to innovative solutions at a digital product engineering company.

Support aeroacoustic integration across aircraft design stages by evaluating noise sources and propagation, defining requirements, developing methods and technologies, monitoring noise during development, and collaborating with multidisciplinary teams to meet aircraft noise and performance targets.

Test and automate Web GUI and API functionality, develop automated test suites, manage defects, and collaborate on improvements.

Architect and develop block-level verification environments using SystemVerilog and UVM; create constrained-random verification suites; run front-end simulations (VCS/NC), analyze code and functional coverage, perform gate-level signoff, debug ASIC logic with designers, and write scripts (Perl/Python/Tcl/shell) to improve verification infrastructure.

Senior-level escalation engineer owning complex L3 issues on Juniper enterprise and data-center switching platforms. Troubleshoots across software, hardware, and design layers, reproduces issues in lab, delivers root-cause analysis and fixes, collaborates with engineering/product teams, authors knowledgebase content, and drives automation and process improvements.

Design and build block-, subsystem-, and full-chip ASIC verification environments using SystemVerilog and UVM. Develop and run constrained-random verification suites with front-end simulators (VCS, NC), analyze code/functional coverage and gate-level simulations, debug designs with logic teams, and create automation scripts (Perl/Python/Shell/Tcl) to drive tape-out readiness.

As a Senior ASIC Design Verification Engineer, you will validate ASIC features using UVM, develop verification environments, and collaborate with teams for debugging and validation.

Design and implement block-level verification environments using SystemVerilog and UVM. Develop and run verification suites with front-end simulators (VCS/Xcelium), analyze code and functional coverage, perform gate-level simulation, debug ASIC issues with designers, and build scripts to improve verification infrastructure.

Design, lead, and mentor development of scalable, secure cloud-based SaaS solutions. Evaluate and integrate new technologies, review designs for compliance with standards, troubleshoot complex system issues, and provide technical leadership across projects. Communicate architecture and design decisions to stakeholders and drive improvements in reliability and time-to-market.

Design, develop, debug, and maintain embedded Linux and RTOS-based software, device drivers, and applications. Collaborate with hardware, ASIC, and firmware teams for integration, optimize performance, produce specifications and tests, and participate in reviews and design discussions.

As an ASIC Verification Engineer, you will architect and develop verification environments, define tests, verify ASIC blocks, and develop scripts to improve verification methodology, collaborating with designers and developers.

Design and develop block-level verification environments using SystemVerilog and UVM. Create verification suites, run front-end simulations (VCS/NC), analyze code and functional coverage, perform gate-level simulation sign-off, debug with designers, and write scripts (Perl/Python/shell) to improve verification infrastructure.

Design and build SystemVerilog/UVM-based block, subsystem, and full-chip verification environments. Create and run constrained-random test suites using simulators (VCS/NC), analyze coverage and gate-level results to drive tape-out readiness. Debug with designers, support software bring-up, and develop scripts (Perl/Python/Shell/Tcl) to automate verification infrastructure.

Maintain, optimize, and automate build systems and related tools. Write and manage makefiles, troubleshoot build issues, and automate build/test/deploy workflows using Python or Shell. Improve CI/CD pipelines and developer experience, collaborate with engineers, and document processes and tools.

Develop, debug, and maintain systems software for the compute plane of an enterprise supercomputing platform. Diagnose Linux/kernel and OS-level issues, own Jira-driven escalations, perform root-cause analysis, and drive fixes. Improve build/release/packaging pipelines, automation/orchestration (Ansible, Kubernetes), security remediation, and developer tooling. Collaborate across teams to raise engineering standards, testing, and operational readiness.

As a Junior Technical Platform Consultant, implement the ServiceNow platform, design automation processes, and enhance customer value through PaaS solutions.

Define test strategies with hardware engineers and develop automated functional and system test solutions for Fixed Networks. Support global manufacturing sites and suppliers in implementing, maintaining, and optimizing test systems. Analyze test data to drive product and process improvements and collaborate to automate product configuration in factories and warehouses.

Build and mature DevOps automation processes and infrastructure. Own the GitLab foundation, including repository standards, CI/CD pipelines, testing, releases, and deployment coordination. Maintain automation and orchestration platforms, define cloud, virtualized, and physical infrastructure requirements, and establish safe AI-assisted automation policies. Partner with security, risk, systems, NOC, and business teams on requirements and deployment. The role requires Python, AWS, Ansible, Terraform, Docker, network automation, and release management expertise.

Lead customer-facing delivery of production-grade data and AI solutions on Databricks. Own architecture, design, implementation, deployment, and technical project outcomes across data engineering, distributed computing, ML/AI, and applications. Embed with enterprise customers, guide adoption, resolve technical issues, collaborate cross-functionally, and create reusable assets. The role requires strong engineering, cloud, communication, stakeholder-management, and customer empathy skills, with 20% travel.

Own ASIC full-chip and block-level integration across SoC and GPU projects. Define design methodologies, stitch RTL units, manage hierarchy, build Python and Perl automation pipelines, debug connectivity and functional issues, and develop reusable integration systems. Collaborate with RTL, verification, physical design, and architecture teams to ensure flow compatibility and design readiness. Improve internal standards and mentor engineers on integration practices.

Leads Gracenote’s India DevOps and Platform Engineering organization, managing multiple teams and AWS infrastructure at scale. Oversees Amazon EKS, managed AWS services, observability, infrastructure automation, CI/CD, incident management, reliability, security, and FinOps. Establishes engineering standards, operational KPIs, talent pipelines, and collaborative practices across global stakeholders while optimizing cloud performance, availability, scalability, and cost.

Develop embedded and server-side Linux applications using modern C++ and Python. Build distributed, API-driven systems with MQTT, Kafka, REST, and gRPC, supported by CI/CD, containerization, and automated testing. Develop cross-platform video analytics pipelines with GStreamer, computer vision algorithms, and edge AI inference runtimes. Implement MLOps workflows for experiment tracking, model monitoring, dataset versioning, and retraining, with observability through Grafana and Prometheus.

Lead the architecture, design, and delivery of next-generation distributed file and object storage systems. Optimize high-performance platforms for AI, analytics, and cluster computing workloads; resolve concurrency, performance, reliability, and Linux system challenges; own technical roadmaps; collaborate with product, validation, and support teams; and mentor engineers while driving architectural standards and enterprise-grade availability.

Leads the planning, design, and delivery of drainage, land development, municipal servicing, roadway, water, wastewater, and stormwater infrastructure projects. Directs multidisciplinary teams, manages client relationships, approvals, budgets, contracts, construction-phase services, quality control, and business development. Provides technical authority in grading, drainage, stormwater, and utility coordination while mentoring staff and integrating sustainable, resilient, and low-impact design solutions.

Performs CPU physical design implementation from RTL to GDSII, including synthesis, floorplanning, placement, routing, clock tree synthesis, timing closure, power optimization, reliability analysis, and signoff verification. Collaborates with architecture, logic, circuit, automation, and EDA vendor teams to improve CPU performance, power, area, design methodologies, and flow automation for high-speed, low-power semiconductor products.