Top Python Jobs in Bangalore

Reposted 11 Days AgoSaved
In-Office
Bengaluru, Bengaluru Urban, Karnataka, IND
Senior level
Senior level
3D Printing
Lead digital design and micro-architecture for high-performance memory interface chips, collaborating with cross-functional teams and mentoring junior engineers.
Top Skills: DdrLpddrPerlPythonSystem VerilogTclVerilog
Reposted 11 Days AgoSaved
In-Office
2 Locations
15-15 Annually
Senior level
15-15 Annually
Senior level
Automotive • Cloud • Energy
Lead verification strategy and execution for ARM-based SoC designs, architect verbatim environments, mentor engineers, and enhance verification efficiency using AI/ML techniques.
Top Skills: AIArm-Based Soc ArchitecturesMakeMlPerlPythonShellSystem VerilogUvm
Reposted 11 Days AgoSaved
In-Office
2 Locations
15-15 Annually
Expert/Leader
15-15 Annually
Expert/Leader
Automotive • Cloud • Energy
Define architectural design and methodologies for digital compute and analog/mixed-signal products; provide technical leadership and mentoring.
Top Skills: C/C++FpgaPython
Reposted 11 Days AgoSaved
In-Office
2 Locations
120K-150K Annually
Expert/Leader
120K-150K Annually
Expert/Leader
Automotive • Cloud • Energy
Lead the design and development of Power Management products focusing on digital design architecture, RTL implementation, and collaboration with cross-functional teams for efficient integration.
Top Skills: AsicPerlPythonRtlSystem VerilogTclVerilogXML
Reposted 11 Days AgoSaved
In-Office
2 Locations
12-12 Annually
Expert/Leader
12-12 Annually
Expert/Leader
Automotive • Cloud • Energy
The Design Manager will lead a new product design team to develop embedded MCU/DSP systems, provide technical guidance, and improve design methodologies.
Top Skills: CC++DspMcuPythonVlsi
Reposted 11 Days AgoSaved
In-Office
2 Locations
12-12 Annually
Senior level
12-12 Annually
Senior level
Automotive • Cloud • Energy
The position involves leading product development for semiconductor devices, focusing on Analog/Digital test strategies and low-cost test solutions, while managing product quality and cost.
Top Skills: Ate PlatformsCC++JavaPython
Reposted 11 Days AgoSaved
In-Office
2 Locations
50K-150K Annually
Senior level
50K-150K Annually
Senior level
Automotive • Cloud • Energy
The role involves defining verification strategies, leading verification activities, developing verification environments, debugging RTL errors, and mentoring engineers in IC verification projects.
Top Skills: C/C++PythonSystemverilogUvm
Reposted 11 Days AgoSaved
In-Office
2 Locations
Expert/Leader
Expert/Leader
Automotive • Cloud • Energy
Lead and manage a mixed-signal verification team, ensuring high-quality verification processes for embedded MCU/DSP systems, and provide technical guidance to global teams.
Top Skills: C/C++FpgaPython
Reposted 11 Days AgoSaved
In-Office
2 Locations
Senior level
Senior level
Automotive • Cloud • Energy
The Senior Principal Digital Design Engineer will lead power management product development, collaborating on digital design architecture, RTL implementation, and post-silicon validation, while ensuring project goals are met.
Top Skills: CanI2CLinPerlPythonRtlSpiSystem VerilogTclVerilogXML
Reposted 11 Days AgoSaved
In-Office
2 Locations
180K-200K Annually
Senior level
180K-200K Annually
Senior level
Automotive • Cloud • Energy
Define verification plans, lead sub-team activities, develop SystemVerilog/UVM environments, debug RTL errors, and support junior engineers.
Top Skills: C/C++PythonSystemverilogUvm
Reposted 11 Days AgoSaved
In-Office
2 Locations
Senior level
Senior level
Automotive • Cloud • Energy
The Principal ASIC/SoC Verification Engineer will ensure functional correctness and quality of semiconductor designs through comprehensive verification planning, advanced testing environments, and collaboration with cross-functional teams, leveraging expertise in ASIC methodologies and power-aware verification techniques.
Top Skills: AhbApbAxiC/C++I2COvmPerlPythonSpiSystemverilogTclUartUvmVerilog Pli
Reposted 11 Days AgoSaved
In-Office
2 Locations
Senior level
Senior level
Automotive • Cloud • Energy
The role involves leading the digital design of power management ICs, collaborating across teams, and ensuring successful implementation from RTL to post-silicon validation.
Top Skills: CanI2CLinPerlPythonRtlSocSpiSystem VerilogTclVerilogXML
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Reposted 11 Days AgoSaved
In-Office
2 Locations
1-5 Annually
Mid level
1-5 Annually
Mid level
Automotive • Cloud • Energy
This role involves driving new product development for semiconductor devices, focusing on testing solutions for Analog/Mixed Signal ICs and collaborating with cross-functional teams.
Top Skills: Advantest AteCC++JavaPythonTeradyne Ate
Reposted 11 Days AgoSaved
In-Office
2 Locations
Expert/Leader
Expert/Leader
Automotive • Cloud • Energy
The Senior Principal Digital IC Design Engineer will lead project activities, mentor engineers, architect and benchmark MCU and DSP systems, and improve design methodologies.
Top Skills: AhbAmba Bus ProtocolsApbPerlPythonSystemverilogVerilog
Reposted 11 Days AgoSaved
In-Office
2 Locations
10-10 Annually
Senior level
10-10 Annually
Senior level
Automotive • Cloud • Energy
The Principal Analog Mixed Signal Verification Engineer will oversee AMS verification for power management products, enhance methodologies, and collaborate across teams to improve verification efficiency and product integration.
Top Skills: Analog Mixed-Signal SimulationsPerlPythonSv Real ModelingSystem VerilogSystem Verilog AssertionsTclVerilogVerilog-AVerilog-Ams
Reposted 11 Days AgoSaved
In-Office
2 Locations
Senior level
Senior level
Automotive • Cloud • Energy
As a Staff ASIC Verification Engineer, you will develop verification plans, create testbenches, and ensure the reliability of semiconductor designs using various verification techniques and languages.
Top Skills: CC++I2COvmPerlPythonSpiSystemverilogTclUpfUvmVerilog Pli
Reposted 11 Days AgoSaved
In-Office
2 Locations
10-10 Annually
Senior level
10-10 Annually
Senior level
Automotive • Cloud • Energy
Lead digital design architecture and RTL implementation for power management ICs. Collaborate across teams, support validation, and improve design processes.
Top Skills: AsicCdcP&RPerlPythonRtlSystem VerilogTclUpfVerilogXML
Reposted 11 Days AgoSaved
In-Office
2 Locations
Senior level
Senior level
Automotive • Cloud • Energy
The Staff Digital Design Engineer will lead digital design architecture, RTL implementation, and collaborate with multidisciplinary teams to develop Power Management ICs, ensuring high quality and performance.
Top Skills: AsicDigital RtlPerlPythonSystem VerilogTclVerilogXML
Reposted 11 Days AgoSaved
In-Office
2 Locations
Senior level
Senior level
Automotive • Cloud • Energy
Lead the design and verification of a digital sub-system within the Treo platform. Collaborate with teams to ensure requirements are met and IP meets ASIL standards. Perform RTL coding and scripting, drive innovation, and provide documentation.
Top Skills: AhbApbAxiCdcDesign CompilerDmaI2CLintPerlPythonRdcSpiSystem VerilogVerilog
Reposted 11 Days AgoSaved
In-Office
2 Locations
Senior level
Senior level
Automotive • Cloud • Energy
The role involves leading digital design architecture, RTL implementation, trade-off analysis, and collaborating with global teams on ASIC development projects. Responsibilities include enhancing design methodologies and managing multiple projects within the team.
Top Skills: Asic DesignPerlPythonRtl DesignSystem VerilogTclVerilogXML
Reposted 11 Days AgoSaved
In-Office
2 Locations
Senior level
Senior level
Automotive • Cloud • Energy
The candidate will lead new product development focusing on analog and digital testing strategies, ATE platform programming, and testing solution automation for semiconductor devices.
Top Skills: Ate PlatformsCC++JavaPython
Reposted 11 Days AgoSaved
In-Office
2 Locations
1-5 Annually
Mid level
1-5 Annually
Mid level
Automotive • Cloud • Energy
The role involves developing low-cost test solutions for Analog/Mixed Signal ICs, defining test requirements, post-silicon validation, and cross-functional collaboration.
Top Skills: AdvantestCC++JavaPythonTeradyne
Reposted 11 Days AgoSaved
In-Office
2 Locations
Senior level
Senior level
Automotive • Cloud • Energy
The Staff Verification Engineer will develop and execute verification plans, create testbenches, and apply methodologies for ASIC designs, ensuring reliability and quality in products.
Top Skills: CC++I2COvmPerlPythonSpiSystemverilogTclUpfUvmVerilog Pli
Reposted 11 Days AgoSaved
In-Office
2 Locations
6-6 Annually
Senior level
6-6 Annually
Senior level
Automotive • Cloud • Energy
The role involves defining and implementing digital blocks, collaborating with teams, scripting for automation, and contributing to debugging and communication efforts.
Top Skills: PerlPythonRtlTcl
Reposted 11 Days AgoSaved
In-Office
Bangalore, Bengaluru Urban, Karnataka, IND
Senior level
Senior level
Information Technology • Business Intelligence • Consulting
The Senior Software Development Engineer will design, develop, and test software systems, focusing on micro-services architecture, APIs, and cloud solutions.
Top Skills: AWSC#C/C++CassandraCi/CdDockerElasticsearchGCPJavaJavaScriptKubernetesAzureMicrosoft Office 365MongoDBNode.jsPython
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