Top Engineering Jobs in Bangalore

Lead service reliability and incident management for global KinetiX systems, reduce MTTR, manage L1/L2 teams and contingent vendors, develop documentation, training, automation, and performance KPIs to improve uptime and reduce escalations.

Senior SoC verification engineer responsible for testbench architecture, SoC-level and IP integration verification, verification methodology improvements, pre- and post-silicon validation (including Palladium), test development, failure debug/root-cause analysis, pattern generation, SOC bring-up, and cross-team collaboration with validation and firmware teams to drive bugs to closure.

Lead manual and automated testing for data-center networking features (BGP, VXLAN, EVPN, Multicast, TRM). Design and implement automation frameworks (Python), define and execute test plans, mentor engineers, coordinate with architects/product/dev, estimate and prioritize test activities, modernize telemetry/CI-CD integrations, and adopt AI/ML tools to improve quality.

Design, build, and maintain multicast routing protocol and infrastructure components for large-scale Cisco platforms. Implement scalable, secure systems, debug complex multithreaded issues, own fixes end-to-end, represent Cisco in standards bodies, collaborate with hardware and test teams, mentor engineers, and contribute to innovation and patents.

Lead a 6–8 person power hardware team to architect and deliver highly reliable board-mounted and front-end power solutions across Cisco products. Drive power architecture, mentor engineers, solve complex design problems, balance cost/performance/scalability, ensure regulatory/EMC/reliability compliance, and collaborate cross-functionally and with customers.

Lead architecture and development of BIOS, BSP, device drivers, and diagnostics for Cisco routing products. Design, test, and validate embedded systems, collaborate across teams to debug prototypes, and provide deep technical consultation influencing product and industry direction.

Lead India silicon-photonics hardware engineering teams to plan, architect, develop, simulate, validate, and deliver optical transceiver electronics and photonic ICs. Drive program schedules, cross-functional collaboration, team development, adoption of AI tools, and ensure best practices in physical design, SI/PI, testing, diagnostics, and manufacturing readiness.

Lead and grow a 10+ engineer hardware validation and compliance team focused on EMC, safety, and regulatory certification. Oversee planning, execution, testing, lab expansion, cross-functional collaboration, resource allocation, risk mitigation, and serve as primary contact for regulatory bodies.

Lead SI/PI analysis across ASIC, package, PCB and system levels: model high-speed SerDes links, analyze PDNs and EM structures, define PCB stack-ups and materials, drive pre/post-layout SI/PI, support lab bring-up and troubleshooting, write guidelines and validation reports, mentor junior engineers, and improve simulation flows and methodologies.

Lead ASIC design verification for high-performance SoCs: define and build UVM/SystemVerilog testbenches, drive DV methodology, perform simulation/emulation/gate-level verification, debug and validate silicon, manage coverage and test plans, mentor engineers, and coordinate cross-functional stakeholders from architecture through bring-up.

Lead RTL/ASIC architecture and implementation for high-performance SoCs. Own specification, RTL development, timing/power optimization, verification (CDC/formal), emulation, system bring-up, code reviews, and team leadership to drive designs to tape-out and FCS.

Lead architecture and long-term technical direction for radio firmware and driver systems across access points. Align cross-functional teams, influence chipset vendors, design next-generation Wi‑Fi features, resolve system-wide wireless issues, and establish best practices for high-performance, scalable wireless systems and AI-native engineering workflows.

Lead technical direction and architecture for radio firmware and driver systems across Cisco access points. Guide multiple teams, influence chipset vendors, resolve system-wide wireless issues, and establish best practices for high-performance, scalable Wi‑Fi systems.

Lead analog/mixed-signal design for silicon photonics driver ICs (100G/200G/400G per Lambda). Define full-chip electrical specs, design datapath and control circuits, verify and debug silicon, collaborate across electrical, optical, digital, SI/PI and product teams, and support lab bring-up, validation, yield improvement, and test strategies.

Lead full-stack development of Meraki MX Dashboard features for SD-WAN & Security. Architect scalable systems, collaborate with firmware/SRE/product teams, optimize performance, own features from design to production, and mentor other engineers.

Lead and mentor engineers building high-performance NPU-based data plane forwarding for carrier-grade routers. Drive technical strategy, architecture, and execution for Layer 2/3 features on Silicon One. Oversee SDLC, debug across hardware/software boundaries, and collaborate on deployment and automation practices including AI-assisted workflows.

Lead and manage the EDA tools support team, provide hands-on technical assistance, optimize EDA environments and compute clusters, manage vendor licenses and updates, implement support processes, monitor system performance, and drive continuous improvement and team development.

Lead ASIC DFT efforts across front-end RTL and backend physical design to define DFT architecture, ATPG/BIST strategies, scan insertion, and test infrastructure. Drive verification, gate-level and timing simulations, post-silicon validation with ATE, and collaborate with vendors and stakeholders for timing closure and electrical/interface specifications.

Design and lead cloud-native, Kubernetes-based CX platform components: microservices, multi-cloud/hybrid orchestration, IaC (Terraform/Ansible), CI/CD (GitHub Actions), Python automation, observability, secrets and AI/LLM integrations while mentoring teams and enforcing security/compliance.

Design, operate, and improve Azure and on‑prem virtualization platforms. Manage Azure governance, hybrid networking, RBAC, and large VMware and Proxmox environments. Implement IaC/GitOps, monitoring, and L3 support; drive migrations, reliability, and platform design improvements.

Design, operate, and evolve Couchbase database platforms; develop automation components; build containerized solutions; support incident resolution and continuous improvement.

Lead global near-realtime data streaming teams to design, build and operate scalable, resilient cloud-native platforms (Kafka/NiFi) on AWS. Balance 60% technical leadership and 40% people management: roadmap alignment, platform roadmap, operational metrics, cross-team partnership, hiring, coaching, and delivering production-grade data integration capabilities at scale.

Lead and grow cloud infrastructure squads responsible for multi-cloud access, entitlements, governance, policy guardrails, and cloud economics. Drive roadmap delivery, architecture, SLOs, CI/CD, AI-assisted automation, platform reliability, and global co-ownership while recruiting and mentoring high-performing engineers.

Lead manufacturing test engineering activities to improve test processes, productivity, quality, and OEE. Develop work instructions and maintenance/calibration plans, manage CAPEX, support new-product/test start-ups and transfers, supervise and train staff, and drive yield, UPH, and process improvement initiatives.

Lead the Data Engineering Solutions Team to develop data pipelines, manage SLAs, and collaborate with product teams to ensure data integrity and innovative solutions.