ASIC DFT Engineering Technical Leader | ATPG, SCAN, MBIST, JTAG | 12+ years, Bangalore

Posted 6 Days Ago
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2 Locations
In-Office
Expert/Leader
Cloud • Information Technology • Internet of Things • Professional Services • Software
The Role
Leads ASIC design-for-test implementation for Cisco Silicon One networking chips. Defines DFT architecture, scan insertion, ATPG, MBIST, JTAG, verification strategies, reusable infrastructure, and timing constraints. Coordinates with RTL, physical design, verification, CAD, vendors, and ATE teams through implementation, signoff, post-silicon validation, and debug. Supports timing closure, gate-level simulation, pattern translation, and production readiness while driving DFT methodology and technical direction across complex ASIC projects.
Summary Generated by Built In
Meet the team:The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry. Your Impact:You will be in the Silicon One development organization as an ASIC Implementation Technical Lead  with a primary focus on Design-for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle.  As a member of this team you will also be involved in crafting groundbreaking next generation networking chips. You will help lead to drive the DFT and quality process through the entire Implementation flow and post silicon validation phases with additional exposure to physical design signoff activities. Key Contributions:
  • Manages the definition, architecture and design of high performance ASICs
  • Owns applications or multiple complex functional areas
  • Oversees reusable code and its applications
  • Creates re-usable code that promotes efficiencies in new ways
  • Defines verification strategies
  • Coordinates with appropriate stakeholders to integrate into PD and DV flows
  • Owns infrastructure and testing environmens
  • Leads and designs the building blocks of multiple channels
  • Applies and drives the design methodology from conception to production
  • Influences and collaborates with teams to ensure specifications and requirements are met
  • Leads technical expertise of a physical design function
  • Interfaces with vendors and design leads on full chip timing closure, PI, and PV
  • Owns the full electrical planning and specifications of electrical interfaces
  • Develops multiple solutions, first test vehicles and performs verification and validation
Minimum Qualifications: 
  • Bachelor's or a Master’s Degree in Electrical or Computer Engineering required with at least 12+ years of experience. 
  • Prior experience with Jtag protocols ( p1500, p1687) , Scan insertion and BIST architectures, including memory BIST and boundary scan. 
  • Prior experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, Test static timing analysis constraints development and timing closure,  
  • Prior experience working with Gate level simulation, including timing based simulations with sdf , debugging with VCS and other simulators. 
  • Post-silicon validation and debug experience; Ability to work with ATE engineers on pattern translation and validation.
  • Scripting skills: Tcl, Python/Perl. 

 

Preferred Qualifications: 
  • Verilog design experience – developing custom DFT logic & IP integration; familiarity with functional verification 
  • • DFT CAD development – Test Architecture, Methodology and Infrastructure

Why Cisco? 

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. 

We are Cisco, and our power starts with you. 


Disclaimer

To ensure that we hire the best talent in the right way, we follow a strict hiring process and recently, Cisco has been made aware of fraudulent recruiters claiming to be from the company. Please be advised that any communication from Cisco about careers will:

  • be in direct response to an application you have submitted through the company career site
  • begin with screening or an interview
  • originate from a Cisco email address, and
  • be conducted across email, phone, or WebEx

Cisco will never make a job offer without conducting an interview process or ask you for money in any way. If you have been requested to apply for a role or have received an offer from a site other than https://careers.cisco.com or cisco.wd5.myworkday.com, do not provide any personal identifying information, including your Aadhaar or other personal identifying number, birth certificate, banking information, driver's license, or passport.

If you are the target of a recruiting scam, consider filing a report with your local law enforcement authorities. Cisco bears no responsibility, and cannot be held liable, for any claims, damages, expenses, or other inconvenience resulting from or in any way connected to recruiting scams.


Skills Required

  • Bachelor's or Master's degree in Electrical Engineering or Computer Engineering
  • 12+ years of relevant experience
  • Experience with JTAG protocols, including IEEE 1500 and IEEE 1687
  • Experience with scan insertion and BIST architectures, including memory BIST and boundary scan
  • Experience with ATPG and EDA tools including TestMax, TetraMax, and Tessent
  • Experience developing test static timing analysis constraints and achieving timing closure
  • Experience with gate-level simulation, timing-based simulations using SDF, and debugging with VCS or other simulators
  • Post-silicon validation and debug experience
  • Ability to work with ATE engineers on pattern translation and validation
  • Scripting skills in Tcl, Python, or Perl
  • Verilog design experience developing custom DFT logic and integrating DFT IP
  • Familiarity with functional verification
  • DFT CAD development experience, including test architecture, methodology, and infrastructure

Cisco Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cisco and has not been reviewed or approved by Cisco.

  • Healthcare Strength — Health coverage is described as broad, with medical options including PPOs, high-deductible plans, and regional HMOs. Feedback suggests robust wellness and mental-health resources, with some locations offering on-site support and second medical opinions.
  • Leave & Time Off Breadth — Time off is highlighted through paid holidays, paid time off, and additional recharge days such as “Days for Me,” with generous volunteer time also mentioned. Feedback suggests these programs help support rest, volunteering, and critical life events.
  • Parental & Family Support — Parental and family support appears extensive, including paid child-bonding leave, family medical leave, and caregiving resources. Observations also point to family-planning assistance and adoption or surrogacy support in some regions.

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The Company
HQ: San Jose, CA
77,500 Employees
Year Founded: 1984

What We Do

Cisco (NASDAQ: CSCO) enables people to make powerful connections--whether in business, education, philanthropy, or creativity. Cisco hardware, software, and service offerings are used to create the Internet solutions that make networks possible--providing easy access to information anywhere, at any time. Cisco was founded in 1984 by a small group of computer scientists from Stanford University. Since the company's inception, Cisco engineers have been leaders in the development of Internet Protocol (IP)-based networking technologies. Today, with more than 71,000 employees worldwide, this tradition of innovation continues with industry-leading products and solutions in the company's core development areas of routing and switching, as well as in advanced technologies such as home networking, IP telephony, optical networking, security, storage area networking, and wireless technology. In addition to its products, Cisco provides a broad range of service offerings, including technical support and advanced services. Cisco sells its products and services, both directly through its own sales force as well as through its channel partners, to large enterprises, commercial businesses, service providers, and consumers.

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