Top Design Engineer Jobs in Hyderabad

Lead Foundation IP quality and product validation for standard cells, IO libraries, and memory compilers. Drive QA strategies and sign-off, perform QA reviews (DRC/LVS, timing, reliability), analyze silicon and customer data, collaborate with design/validation/customers, and mentor engineers to improve manufacturability and reliability.

The Senior Engineer will focus on full-chip functional verification of non-volatile memory designs, developing verification plans, TestBench development, and collaborating with the digital design team for accurate designs.

Lead verification efforts for full-chip memory designs (DRAM/SRAM) including gate-level simulation, timing/setup-hold analysis, UVM/SystemVerilog testbench development, coverage-driven regression, and AI-enabled automation to improve verification productivity while collaborating with global design teams.

Design and automate scribe test structures and layouts to support R&D and manufacturing integration. Develop and maintain EDA automation flows, PCELL-based device layouts, and DUT generation. Collaborate with process, mask, device, reliability, and characterization teams, validate documentation/parametrics, drive data-driven optimization, and mentor junior engineers.

Lead design and validation of complex electrical protection, control, metering, and automation systems. Perform component selection (CT/PT), develop protection logic, ensure standards compliance, create CAD panel layouts, manage BOMs in SAP, support field issues, mentor junior engineers, and coordinate cross-functional integration and documentation.

Oversee verification of custom memory circuit designs, simulate and debug pre-silicon full chip designs, and develop test cases to ensure functionality and correct performance of DRAM and emerging memory architectures.

The Principal Engineer will guide end-to-end verification of IP designs, ensure quality and coverage in verification plans, collaborate globally, and utilize AI tools to enhance verification productivity.

Design and maintain standard cells for DRAM products; collaborate on architecture, perform characterization, and develop automation tools; enhance design using AI.

The Staff Verification Design Engineer is responsible for verifying block and chip designs, developing tests, running simulations, and ensuring tape-out quality for semiconductor projects.

Lead DFT and test engineering for chip tape-outs: scan insertion, ATPG/MBIST/JTAG flows, gate-level/SDF simulation, memory BIST, STA, post-silicon ATE bring-up and debug. Coordinate across design, synthesis, physical design, and STA teams. Use industry tools (preferably Cadence/Tessent) and Perl/Tcl scripting to ensure successful tape-out.

The Principal IO Mixed Signal Design Engineer will integrate and verify mixed signal blocks in high-speed IOs for FPGAs, develop custom circuits, and support post-tapeout phases.

The IO Mixed Signal Design Engineer will integrate and verify mixed signal blocks in FPGA's, develop analog circuits for IO applications, work with design requirements, optimize circuits, and support post-tapeout phase.

The FPGA Senior Design Engineer develops video and image processing IPs, implements RTL designs, verifies them, and integrates solutions within Microchip FPGA products.

As a Senior Design Verification Engineer, you will develop verification plans, build TestBenches, and ensure functional coverage for non-volatile memory designs.

Develop and support verification activities for DRAM and emerging memory designs, leveraging automation and AI tools to improve efficiency and coverage. Collaborate with teams to integrate methodologies.

The Staff Engineer will oversee verification activities for DRAM design, utilizing AI tools and simulation to enhance efficiency and provide support for design projects.

Responsible for developing and integrating foundry rule decks, QA of PDKs, and automating verification processes using various programming languages.

The Software Design Engineer will develop software solutions while collaborating with various engineering teams, integrating hardware and software, and optimizing products for consumer use.

The role involves designing and verifying CMOS test structures, collaborating with global teams, improving design accuracy, and providing technical advice.

The Senior Principal Analog Design Engineer will lead the design and development of analog integrated circuits, mentoring others and overseeing the full lifecycle from concept to silicon validation in automotive and industrial applications.

The role involves RTL verification of memory technologies, guiding verification efforts, developing methodologies, and optimizing using AI tools. Requires collaboration on complex chip design projects.

The Sr. Principal Design Engineer at Cadence will lead SOC verification, develop test plans, and mentor engineers, ensuring high-quality execution of complex projects.

The role involves RTL design for chiplet-based chips, optimizing for timing and power, collaborating with verification and physical design teams, and providing guidance to junior engineers.

Perform structural analysis and design of water/sewage treatment and non-plant steel and concrete structures to Eurocodes. Build analytical models using Robot, STAAD, IDEA StatiCa; prepare calculations, reports, loads and stresses under senior supervision. Provide design input to CAD/BIM, coordinate drawings, and ensure compliance with Arcadis systems and H&S regulations.

The Principal Engineer will lead ASIC physical design projects, focusing on implementation and analysis with a strong emphasis on low power design techniques and verification processes.