Top Design Engineer Jobs in Hyderabad

The Sr. Technical Lead, Software Engineer at Vertafore leads teams to deliver technical solutions, mentors staff, and implements software improvements using OOPs, C#, JavaScript, and other technologies, ensuring high-quality code and customer success.

The Principal Engineer is responsible for designing, analyzing digital circuits for memory products, managing verification, guiding new hires, and ensuring manufacturability through collaboration.

The role involves the verification and analysis of memory circuit designs, guiding verification efforts, and developing testing methodologies collaboratively. Candidates should possess skills in circuit analysis, simulation, and scripting.

The SR Engineer in Design Verification will simulate, analyze, and debug pre-silicon chip designs, develop test cases, and enhance verification methodologies for DRAM and emerging memory architectures.

The Senior Memory Circuit Design Verification Engineer executes verification using FastSpice tools, performs analog SPICE simulations, and collaborates globally to ensure timely design sign-offs and improvements in methodologies.

The role involves owning functional verification for designs, developing tests, debugging failures, driving coverage closure, and leading junior engineers in verification methodologies.

The Senior Engineer will design and validate on-chip controllers and mixed signal circuitry in NAND FLASH chips, performing RTL design, firmware coding, and full-chip verification.

The Staff Engineer Design will engage in block and sub-system design, timing optimization, mentor junior designers, and collaborate on full-chip floorplanning while using various simulation tools.

The Lead Physical Design Engineer will manage and execute physical design tasks for high-performance semiconductor ICs, ensuring design integration and resolving issues related to power efficiency, timing, and area.

The Staff Verification Design Engineer will perform semiconductor verification, focusing on block and chip-level testing, develop strategies, and enhance environments for improved scalability.

The Principal DRAM Power Integrity Engineer develops methodologies for EMIR analysis, collaborates across teams, and maintains EMIR analysis tools and dashboards.

The Engineer will develop and standardize methodologies for EMIR analysis, perform electrical analysis, collaborate with design teams, leverage AI tools, and maintain dashboards for tracking results across DRAM products.

The Senior Engineer will design and maintain standard cells for DRAM products, collaborate on architecture development, and perform characterization and quality analysis of cells. Development of automation tools and engagement in AI-assisted design improvements are also key responsibilities.

The Engineer, Design role involves full-chip functional verification of memory designs, developing verification plans, TestBench development in SystemVerilog, and collaborating with teams to debug and enhance memory functionalities.

The Staff Engineer Design role involves block level and full-chip design, timing optimization, circuit optimization, and mentoring junior engineers in semiconductor design, particularly focusing on Flash technology and CMOS physics.

The role involves defining verification scope, developing testbenches, executing tests, debugging RTL, and collaborating on verification methods for DRAM technology.

Design RTL for High-Speed I/O IP (UFS, Ethernet, PCIe, USB) for automotive SoCs. Define micro-architecture, implement RTL, drive verification, close timing with VLSI/physical teams, and support silicon validation. Collaborate across HW architects, verification, timing, and physical design to meet performance, power, and area targets.

Design and implement RTL for BOOT and power-management subsystems on automotive and client SoCs. Own micro-architecture, develop RTL, drive verification, close timing, collaborate with architects, timing/VLSI/physical teams, and support silicon validation.

Develop software solutions for Surface devices, collaborating with engineers and optimizing product designs for high-volume consumer products.

Define hardware architectures for AI inference SoCs, oversee design from specification to debug, and collaborate with various teams for performance analysis and validation.

The Staff Verification Design Engineer is responsible for block and chip-level verification, creating verification strategies, and supporting post-silicon debug and validation efforts.

The Staff Verification Design Engineer performs RTL and AMS verification, develops tests, improves verification processes, and collaborates closely with the design team.

Design and implement semicustom digital blocks (control logic, BIST, DfT); drive RTL-to-GDS flows including synthesis, CTS, P&R and timing closure; perform functional and gate-level verification; develop testbenches and scripting; support silicon bring-up, post-silicon validation, and continuous improvement of semicustom design flows.

The Senior Engineer will oversee verification activities for DRAM design, leveraging AI tools, developing test cases, and improving debug efficiency in digital/mixed signal verification.

The role involves guiding verification efforts for memory designs, developing test cases, and collaborating internationally on verification methodologies and automation.