Top Design Engineer Jobs in Hyderabad

The Principal DRAM Power Integrity Engineer develops methodologies for EMIR analysis, collaborates across teams, and maintains EMIR analysis tools and dashboards.

Supports DRAM and emerging-memory design verification through test-case development, testbench and test-vector maintenance, simulation, regression testing, functional coverage analysis, and pre-silicon debug. Uses AI-driven workflows and automation to accelerate verification and improve debugging. Collaborates internationally on verification methodologies and environments while applying SPICE, Verilog, gate-level analysis, and CMOS circuit knowledge.

Leads end-to-end ASIC and SoC development, including microarchitecture, RTL design, IP and subsystem integration, CDC, lint, synthesis, timing, power analysis, and post-silicon debug. Collaborates with architecture, verification, firmware, DFT, synthesis, and physical design teams. Defines interfaces, supports design reviews, mentors engineers, and applies approved AI-enabled workflows to improve SoC development productivity and quality.

Leads the architecture, engineering, governance, and highest-level support of enterprise IBM i and IBM Power infrastructure. Responsibilities include platform design, upgrades, performance tuning, high availability, backup and disaster recovery, IBM storage administration, security, automation, documentation, compliance, and infrastructure transformation. The role serves as the senior escalation point for complex IBM i, Power Systems, storage, and performance issues while providing technical leadership across infrastructure teams.

Own verification and end-to-end analysis of full-chip gate-level DRAM designs. Develop SystemVerilog and UVM testbenches, test cases, stimuli, test vectors, regressions, and coverage improvements. Simulate, debug, and analyze pre-silicon block and full-chip designs using digital, mixed-signal, and SPICE tools. Apply AI-based automation to accelerate verification while validating outputs against specifications, simulations, waveforms, assertions, and coverage. Guide newer engineers and collaborate globally on verification methodologies and environments.

The Staff Engineer Design role involves block level and full-chip design, timing optimization, circuit optimization, and mentoring junior engineers in semiconductor design, particularly focusing on Flash technology and CMOS physics.

The Staff Engineer Design will engage in block and sub-system design, timing optimization, mentor junior designers, and collaborate on full-chip floorplanning while using various simulation tools.

The Senior Engineer will design and maintain standard cells for DRAM products, collaborate on architecture development, and perform characterization and quality analysis of cells. Development of automation tools and engagement in AI-assisted design improvements are also key responsibilities.

Designs electrical systems for building and infrastructure projects, including LV/MV distribution, lighting, grounding, lightning protection, calculations, equipment selection, drawings, specifications, and cost estimates. Performs design reviews, quality control, interdisciplinary coordination, and technical stakeholder discussions while supporting project budgets and schedules.

Leads the design, governance, automation, and L3 support of enterprise DNS, domain management, and core network services across cloud, datacenter, and corporate environments. Manages Route 53, Microsoft DNS, BIND, DNSSEC, domain portfolios, and Active Directory-integrated DNS. Develops automation with scripting, APIs, and Infrastructure as Code, applies AI-assisted infrastructure solutions, supports hybrid-cloud networking, and establishes technical standards, documentation, and governance.

Develop and support embedded and interface software for semiconductor manufacturing equipment. Work across bare-metal and Linux environments using C, C++, and Python to interface with custom hardware and microcontrollers. Collaborate with software, electrical, controls, and mechanical engineers on equipment design, PCB and schematic review, circuit prototyping, debugging, testing, documentation, and system integration. Support existing equipment and use laboratory instruments for design bring-up and characterization.

Support DRAM design verification by developing test cases, test benches, test vectors, and verification environments. Simulate, analyze, and debug pre-silicon block-level and full-chip designs; run regressions and improve functional coverage. Use AI-based tools, agentic workflows, and automation to accelerate verification and debugging. Collaborate internationally on verification methodologies for DRAM and emerging memory products.

The Principal Engineer will lead NAND Flash Memory design, manage chip verification processes, and collaborate across multiple engineering domains.

Lead verification architecture and methodology for next-generation DDR memory designs. Develop UVM-based testbenches, verification plans, coverage strategies, and sign-off criteria. Integrate AMS co-simulation and AI/ML-assisted tools for regression, failure classification, and predictive analysis. Mentor verification engineers, collaborate with build teams and EDA vendors, and drive automation and debugging efficiency.

Leads silicon design validation for NAND Flash products, including development, simulation, bench testing, characterization, qualification, and silicon debugging. Heads technical task forces, drives issue resolution, performs wafer and tester measurements, and collaborates with R&D, design, manufacturing, business, and quality teams. The role requires strong analog and mixed-signal VLSI expertise, memory architecture knowledge, data analysis, and programming or scripting capabilities.

Design and optimize DRAM memory arrays, peripheral logic, and analog circuits. Lead layout floor-planning, placement, routing, circuit-level verification, timing, power, reliability, parasitic, and silicon analysis. Develop semicustom memory methodologies and integrate AI-driven automation into simulation, verification, and sign-off flows. Collaborate with CAD, EDA, and software teams while driving innovation for future memory generations.

Owns formal verification strategies for complex processor modules, including identifying suitable blocks, creating test plans, implementing Chisel-based verification environments, applying formal techniques, debugging RTL, automating verification, maintaining assertion libraries, and guiding team members. Requires extensive digital hardware formal verification experience, familiarity with VC Formal or JasperGold, and knowledge of VHDL, Verilog, and SystemVerilog.

Own verification strategy and execution for out-of-order CPU cores and cache/memory subsystems from architecture through tape-out. Architect UVM testbenches, create test plans, develop scoreboards and protocol checkers, drive coverage closure, apply assertions and formal verification, debug complex pipeline, ordering, coherence, and TLB issues, and mentor junior engineers. Collaborate with architecture, RTL, software, performance, and post-silicon teams.

Design, implement, simulate, and validate analog and mixed-signal circuits for NAND Flash across the full design lifecycle. Responsibilities include transistor-level optimization, silicon issue analysis, cross-functional collaboration, technical coordination, and development of AI-assisted engineering workflows for simulation, verification, automation, and documentation.

Leads ASIC physical design implementation for processors, controllers, and enterprise SSD architectures. Responsibilities include floorplanning, placement, clock-tree synthesis, routing, extraction, timing closure, IR/EM analysis, physical verification, PPA optimization, and tapeout. The role requires advanced-node experience, tool expertise, independent subsystem leadership, AI-assisted closure skills, and strong collaboration and analytical abilities.

Designs and optimizes DRAM memory arrays, peripheral logic, and analog circuits. Responsibilities include schematic optimization, layout, floor-planning, placement, routing, circuit-level verification, parasitic analysis, timing, power and reliability assessment, and semiconductor design sign-off. The role develops semicustom memory methodologies and integrates AI-driven automation into simulation and verification workflows while collaborating with CAD, EDA, and software teams to advance future memory generations.

Design and optimize DRAM memory arrays, peripheral logic, and analog circuits. Lead semicustom memory design methodology, layout, floor-planning, routing, circuit verification, parasitic analysis, and reliability studies. Apply AI-assisted tools and automation to improve schematic optimization, simulation, verification, and silicon-learning workflows. Collaborate with CAD, EDA, and software teams to integrate AI-driven design flows and advance future memory generations.

Own physical design methodology and top-level timing closure for GPU and SoC designs. Responsibilities include floorplanning, placement, clock-tree synthesis, post-route optimization, static timing analysis, EMIR analysis, ECO and DRC closure. Build and improve EDA tool flows, automate processes with Python and Tcl, troubleshoot design and tool issues, optimize PPA and turnaround time, and collaborate with design teams and EDA vendors across tapeouts.

Develop FPGA design automation and synthesis software using modern C++. Design algorithms and optimization techniques for timing, area, power, and quality-of-results improvements. Analyze FPGA designs, integrate physical synthesis capabilities, debug complex systems, and build scalable high-performance components in Linux. Collaborate with architecture, place-and-route, timing analysis, and QA teams while contributing to code reviews, regression infrastructure, validation, and AI-assisted test generation.

Architects, integrates, validates, and debugs design-for-test features for SoCs and subsystems. Responsibilities include scan insertion, BIST, boundary scan, ATPG pattern generation, coverage and DRC analysis, timing and gate-level simulation, silicon diagnostics, and ATE handoff. The role collaborates with design, verification, and manufacturing teams, leads DFT integration, resolves flow issues, makes technical decisions, and mentors junior engineers.