Top Design Engineer Jobs in Hyderabad

Design, implement, and optimize analog and power-management IPs (bandgaps, references, regulators, amplifiers) for advanced DRAM process nodes. Perform parasitic modeling, verification with industry simulators, oversee layout and tape-out activities, collaborate with cross-functional teams (test, process, product) to ensure manufacturability and drive future memory innovations.

Lead verification architecture and methodology for next-generation DDR memory designs. Develop UVM-based testbenches, verification plans, coverage strategies, and sign-off criteria. Integrate AMS co-simulation and AI/ML-assisted tools for regression, failure classification, and predictive analysis. Mentor verification engineers, collaborate with build teams and EDA vendors, and drive automation and debugging efficiency.

The Senior Engineer will design and maintain standard cells for DRAM products, collaborate on architecture development, and perform characterization and quality analysis of cells. Development of automation tools and engagement in AI-assisted design improvements are also key responsibilities.

The Staff Engineer Design role involves block level and full-chip design, timing optimization, circuit optimization, and mentoring junior engineers in semiconductor design, particularly focusing on Flash technology and CMOS physics.

The Staff Engineer Design will engage in block and sub-system design, timing optimization, mentor junior designers, and collaborate on full-chip floorplanning while using various simulation tools.

Designs and validates optical systems such as EO/IR cameras, night-vision optics, spectrometers, laser systems, lenses, and telescopes. Responsibilities include requirements definition, Zemax modeling, optimization, tolerance analysis, manufacturing sensitivity studies, optical drawings, opto-mechanical collaboration, vendor coordination, fabrication and alignment support, laboratory and environmental testing, customer presentations, proposal input, and technical risk mitigation. Travel across India and Southeast Asia is required for trials, demonstrations, and customer support.

Performs static and dynamic IR-drop and electromigration analysis for advanced semiconductor nodes. Drives IREM fixes through placement, routing, and physical verification signoff cycles; optimizes full-chip and block-level power delivery networks, including power meshes and RDL structures. Develops TCL, Python, Perl, and Shell automation scripts to improve signoff efficiency. Collaborates cross-functionally to resolve IR hotspots, EM violations, and power-grid bottlenecks while considering placement, routing, congestion, timing ECOs, and power integrity.

The Principal DRAM Power Integrity Engineer develops methodologies for EMIR analysis, collaborates across teams, and maintains EMIR analysis tools and dashboards.

The Engineer will develop and standardize methodologies for EMIR analysis, perform electrical analysis, collaborate with design teams, leverage AI tools, and maintain dashboards for tracking results across DRAM products.

The Design Verification Engineer will own functional verification, develop test plans, create SystemVerilog testbenches, run simulations, and mentor junior engineers while improving verification methodologies.

Define hardware architectures for AI inference SoCs, oversee design from specification to debug, and collaborate with various teams for performance analysis and validation.

Design and own RTL development for an AI-enabled RISC-V CPU core, including microarchitecture, vector/matrix engines, performance/power/area optimization, and verification support. Collaborate with cross-functional teams for timing, reliability, testability, and SoC integration.

The Staff Verification Design Engineer is responsible for block and chip-level verification, creating verification strategies, and supporting post-silicon debug and validation efforts.

The Staff Verification Design Engineer performs RTL and AMS verification, develops tests, improves verification processes, and collaborates closely with the design team.

Lead physical design implementation and integration from block to full-chip level, covering floorplanning, synthesis, placement, CTS, routing, static timing, physical verification, formal equivalence, power/IR-drop and EM analysis. Drive flow development/automation, evaluate technology/IP/vendors, support tapeouts in leading-edge nodes, report status/risks, and collaborate with program teams. Occasional travel may be required.

Design and review mechanical systems for high-density GPU data centers across APAC. Evaluate air- and liquid-cooled architectures, assess cooling capacity, airflow, and power density, coordinate with electrical, construction, commissioning and operations teams, and ensure maintainability and alignment with Nebius standards.

Lead end-to-end physical design for complex SoCs and IP blocks from RTL handoff through GDSII and tape-out. Responsibilities include floorplanning, synthesis, placement, routing, CTS, timing closure, PPA optimization, sign-off, constraint management, automation, process bring-up, and cross-functional integration. The role also mentors junior engineers and collaborates with foundries, vendors, and design teams on advanced low-power, multi-clock, and multi-voltage designs.

Lead design and implementation of enterprise software solutions for clients, develop new features, troubleshoot production issues, manage deployments, mentor engineers, and coordinate cross-functional teams to meet delivery timelines and quality standards.

The Principal Engineer is responsible for designing, analyzing digital circuits for memory products, managing verification, guiding new hires, and ensuring manufacturability through collaboration.

Design and automate scribe test structures and layouts to support R&D and manufacturing integration. Develop and maintain EDA automation flows, PCELL-based device layouts, and DUT generation. Collaborate with process, mask, device, reliability, and characterization teams, validate documentation/parametrics, drive data-driven optimization, and mentor junior engineers.

Lead development, automation, and maintenance of physical implementation EDA flows; optimize PPA and TFM for IP/SoC in advanced nodes; manage regression infrastructure; perform digital implementation using Cadence tools; automate full-chip floorplanning with AI; collaborate across teams and lead design efforts.

The Staff Verification Design Engineer is responsible for verifying block and chip designs, developing tests, running simulations, and ensuring tape-out quality for semiconductor projects.

Design and execute RTL verification for DRAM IP: define scope and strategy, build SV-UVM testbenches, run directed and constrained-random regressions, close functional/code coverage, debug RTL/testbench issues, and collaborate with designers. Maintain verification flows and tools, use scripting to automate regressions, and proactively adopt approved AI tools to improve verification productivity.

The Sr Engineer in Die Design Engineering will oversee TSV & 3D Integration, collaborate across teams, and ensure die design meets advanced packaging requirements.

The Staff Engineer will oversee verification activities for DRAM design, utilizing AI tools and simulation to enhance efficiency and provide support for design projects.