Top Design Engineer Jobs in Hyderabad

Design, implement, debug, and maintain real-time embedded firmware for resource-constrained Bluetooth wireless systems. Own features from design through production, optimize memory, power, and CPU usage, troubleshoot firmware-hardware-protocol issues, and contribute to wireless coexistence solutions. Collaborate with cross-functional engineering teams, participate in design and code reviews, support product qualification, and mentor junior engineers.

Leads digital design verification and architecture for key SoC blocks through ASIC tapeout. Develops microarchitectures optimized for power, performance, and area; applies lint, CDC, formal equivalence, ECO, and scripting flows; collaborates with geographically distributed teams; mentors engineers; and may support post-silicon debugging.

The role involves guiding verification efforts for memory designs, developing test cases, and collaborating internationally on verification methodologies and automation.

The Design Engineer will assist in developing new product designs, manage the layout process, perform verification, and improve design quality.

Lead end-to-end RTL design and integration for complex SoC, subsystem, and IP blocks. Define micro-architecture, develop Verilog/SystemVerilog RTL, and drive design closure across verification, physical design, DFT, firmware, and architecture teams. Address timing, power, area, clocking, reset, lint, CDC, RDC, synthesis, formal, and low-power requirements. Debug simulation, emulation, silicon, and customer issues; review specifications and designs; mentor engineers; and improve reusable IP and design methodologies.

Designs and validates optical systems such as EO/IR cameras, night-vision optics, spectrometers, laser systems, lenses, and telescopes. Responsibilities include requirements definition, Zemax modeling, optimization, tolerance analysis, manufacturing sensitivity studies, optical drawings, opto-mechanical collaboration, vendor coordination, fabrication and alignment support, laboratory and environmental testing, customer presentations, proposal input, and technical risk mitigation. Travel across India and Southeast Asia is required for trials, demonstrations, and customer support.

Design and verify digital integrated circuits for TI products, including processor, memory-management, multicore, and cache architectures. Responsibilities include defining specifications, analyzing architecture trade-offs, participating in design reviews, supervising IC layouts, developing behavioral models, characterizing prototypes, creating test specifications, and coordinating with test and product engineering teams to support product releases.

The Design Verification Engineer will own functional verification, develop test plans, create SystemVerilog testbenches, run simulations, and mentor junior engineers while improving verification methodologies.

Designs high-speed mixed-signal communication chips and digital circuits interfacing with analog circuitry. Responsibilities include RTL coding, simulation, synthesis, timing closure, verification, evaluation, and debugging at circuit and behavioral levels. The role also develops test methods, specifications, application materials, data sheets, and demo boards while collaborating closely with analog and digital engineering teams.

Designs high-speed mixed-signal communication chips and digital circuits interfacing with analog circuitry. Responsibilities include RTL coding, simulation, synthesis, timing closure, verification, evaluation, debugging, test method development, specifications, application materials, datasheets, and demo boards. Collaborates closely with analog and digital engineering teams to solve complex problems and deliver projects on time.

Define hardware architectures for AI inference SoCs, oversee design from specification to debug, and collaborate with various teams for performance analysis and validation.

Design and review mechanical systems for high-density GPU data centers across APAC. Evaluate air- and liquid-cooled architectures, assess cooling capacity, airflow, and power density, coordinate with electrical, construction, commissioning and operations teams, and ensure maintainability and alignment with Nebius standards.

Lead design and implementation of enterprise software solutions for clients, develop new features, troubleshoot production issues, manage deployments, mentor engineers, and coordinate cross-functional teams to meet delivery timelines and quality standards.

The Principal Engineer is responsible for designing, analyzing digital circuits for memory products, managing verification, guiding new hires, and ensuring manufacturability through collaboration.

Lead development, automation, and maintenance of physical implementation EDA flows; optimize PPA and TFM for IP/SoC in advanced nodes; manage regression infrastructure; perform digital implementation using Cadence tools; automate full-chip floorplanning with AI; collaborate across teams and lead design efforts.

The Staff Verification Design Engineer is responsible for verifying block and chip designs, developing tests, running simulations, and ensuring tape-out quality for semiconductor projects.

Own block- and subsystem-level design verification for out-of-order RISC-V CPU cores. Develop SystemVerilog/UVM testbenches, constrained-random and directed tests, scoreboards, reference models, assertions, and coverage strategies. Verify pipelines, memory systems, caches, TLBs, coherence, speculation, ordering, exceptions, and replay. Analyze regressions, debug complex failures, collaborate with architecture and RTL teams, improve methodology, and mentor junior engineers.

The Staff Engineer will oversee verification activities for DRAM design, utilizing AI tools and simulation to enhance efficiency and provide support for design projects.

Develop and maintain EDA flows and automation for physical ASIC implementation. Optimize PPA for IP cores across advanced foundries, manage regression infrastructure, perform digital implementation with Cadence tools, and create scripts (Python/Tcl/AI) to reduce design turnaround and debug synthesis/LEC issues.

Lead board and IC package design for high-performance SoCs/MCUs from block level to product release. Drive teams, define specifications, perform SI/PI and power design, support SoC bring-up, and liaise with manufacturing for DFM/DFX and packaging delivery.

Own verification strategy and execution for complex CPU, SoC, and IP blocks from architecture through tape-out. Architect SystemVerilog/UVM testbenches, develop constrained-random and coverage-driven environments, apply assertions and formal verification, lead debug and coverage closure, and improve regression infrastructure. Provide technical leadership, mentor engineers, review verification plans, and collaborate with architecture, RTL design, software, validation, and post-silicon teams.

Own design verification strategy and execution for out-of-order RISC-V processor cores and cache/memory subsystems through tape-out. Architect UVM testbenches, create constrained-random tests, develop scoreboards and protocol checkers, drive functional and code coverage closure, apply assertions and formal verification, debug complex ordering and coherence issues, and mentor junior engineers while collaborating across architecture, RTL, software, and post-silicon teams.

Own block- and subsystem-level design verification for out-of-order CPU cores. Develop SystemVerilog/UVM testbenches, constrained-random tests, scoreboards, reference models, assertions, and coverage strategies. Verify execution pipelines, memory systems, caches, TLBs, coherence, memory ordering, exceptions, and speculative execution. Debug regressions, triage failures, collaborate with architecture and RTL teams, improve verification methodology, and mentor junior engineers.

Designs and integrates ASIC blocks for next-generation Microchip FPGA SoCs, covering microarchitecture, RTL development, third-party IP integration, compiled memories, MBIST, synthesis, static timing analysis, and production release. Collaborates with DFT, place-and-route, verification, and geographically distributed teams. Requires expertise in Verilog/SystemVerilog, digital design flows, on-chip buses, microprocessors, and multiple high-speed or communication interfaces.

The role involves owning functional verification for designs, developing tests, debugging failures, driving coverage closure, and leading junior engineers in verification methodologies.