Top Design Engineer Jobs in Hyderabad

Define and deploy physical-design methodology for advanced SoCs/MCUs (3/5/16/22nm). Own flows for floorplan, power-plan, P&R, UPF, CTS, and formal/physical verification. Collaborate with cross-functional teams and EDA vendors, resolve blocking issues, benchmark tools, and automate flows using Perl/Tcl/Python to meet low-power, area, and timing convergence goals.

The role involves leading the development of complex mixed Signal SoCs, focusing on high-speed designs, signoff implementations, and working with advanced technologies like 16 nm and 7 nm processes.

Lead end-to-end physical design for chiplet-based MCU SoCs: floorplanning, placement, power planning, signal integrity, routing, timing closure, and physical verification. Optimize mature-node low-power, cost-efficient designs, collaborate with architecture, packaging, RTL, verification and DFT teams, define best practices and evaluate tools and AI/ML flows to improve productivity and manufacturability.

Own and drive solution architecture and roadmap for cloud SaaS product features. Translate business requirements into resilient designs, validate engineering implementations, support Scrum teams, maintain architecture artifacts, participate in governance, and run PoCs to promote innovation while ensuring non-functional requirements and security standards.

Lead the RTL design of MCU SoCs, ensuring specifications are met, support integration, verify designs, and collaborate with teams.

As a Design Verification Engineer, you will verify designs for analog and mixed signal electronics, develop verification strategies, and collaborate with teams throughout the development process.

As a Design Verification Engineer, you will ensure the quality of advanced RADAR products, involving verification of IP, Subsystem, and SoC designs, collaborating with cross-functional teams, and developing robust verification methodologies.

The role involves overseeing verification of radar product designs, collaborating with teams to ensure quality, adherence to standards, and leading verification projects. Responsibilities include defining verification strategies, managing DV environments, and facilitating post-silicon verification.

The role involves verifying digital blocks in mixed-signal SoCs, developing testbench architecture, and collaborating across global teams to ensure design integrity.

The role involves verification of digital blocks in SOCs, developing testbenches, mentoring junior engineers, and post-silicon activities. Requires strong experience in digital design and verification methodologies.

Design and develop advanced analog and mixed-signal integrated circuits, providing technical leadership and mentorship, while collaborating with cross-functional teams.

Design, implement, and test embedded C/C++ software for Wi‑Fi ICs. Lead architecture and feature delivery, integrate with hardware and protocol stacks, write tests and automation, debug using JTAG/GDB/logic analyzers, mentor engineers, and improve processes for performance and reliability.

Develop and optimize embedded software for smart home and IoT applications, mentor junior engineers, and lead technical projects.

The Staff Digital Design Engineer is responsible for RTL front-end design, IP and full chip integration, and providing technical guidance while ensuring closure of owned blocks through collaboration with teams.

Lead RTL-to-gate implementation and timing closure for complex SoCs. Perform synthesis and sign-off STA, develop MMMC constraints, optimize timing (ECOs, buffering, sizing), automate flows, and mentor junior engineers.

The Analog Engineer 3 leads analog circuit engineering, develops architectures, manages circuit implementations, and provides technical guidance for semiconductor products.

Design, implement, and test embedded software for Wi-Fi ICs. Collaborate with cross-functional teams, maintain code quality, and debug issues.

You will manage full chip and chiplet level STA convergence, optimize the design processes, and collaborate with various engineering teams for constraints definition and implementation.

The role involves leading SoC DV execution, improving DV processes, collaborating on test plans, debugging simulations, and architecting testbenches using UVM and C.

Lead SoC design verification execution, collaborate on test plans, debug failures, and implement simulation testbenches using UVM and C. Work with silicon and firmware teams for validation.

The Staff Engineer leads analog and mixed-signal block design, conducts design reviews, mentors junior engineers, and develops methodologies for advanced technology applications.

As a Senior Digital Verification Engineer, lead verification planning for digital and mixed-signal designs, innovate verification environments, and mentor junior engineers.

Lead implementation of RTL-to-GDS flows for multiple IP blocks, develop/automate flows, plan resources for implementation and signoff, support and train customers, and resolve design and deployment issues.