Top Design Engineer Jobs in Hyderabad

Design and optimize DRAM memory arrays, peripheral logic, and analog circuits. Lead layout, floorplanning, placement, routing, and circuit-level verification. Integrate AI-driven design and automation with CAD/EDA tools, perform parasitic extraction and simulations, and drive methodology improvements for future memory generations.

The Memory Circuit Design Engineer will design and optimize memory circuits, manage layout processes, verify designs, and collaborate across teams to enhance product manufacturability.

Design digital IP blocks from microarchitecture to RTL, oversee physical development and verification processes, and mentor teams for DRAM technology innovation.

Responsible for logic design of on-chip memory controllers, project management, verification processes, and team mentoring at Micron Technology.

Design and validate on-chip controller and mixed-signal circuitry for NAND flash. Responsibilities include architecture development, transistor-level design, RTL implementation, firmware for NAND operations, full-chip Verilog validation, test planning, system integration, and use of design/verification CAD tools. AI tools encouraged to automate workflows.

The Design Engineer will assist in developing new product designs, manage the layout process, perform verification, and improve design quality.

Design and optimize DRAM memory arrays, peripheral logic, and analog circuits. Drive layout, floor-planning, placement, routing, and circuit-level verification. Integrate AI-driven flows and collaborate with CAD/EDA teams to improve simulation, parasitics, and design sign-off for future memory generations.

Design digital IP blocks from microarchitecture to RTL and support physical hardware development. Lead SoC integration and verification (CDC, lint, synthesis, STA, power), oversee layout and floor-planning, apply AI/ML tools to accelerate RTL optimization and testbench generation, collaborate with CAD/EDA/software and cross-functional teams, mentor engineers, and drive memory design methodology and future-generation innovations.

Design and deliver digital memory IP from microarchitecture through RTL, integration, and physical implementation. Drive SoC integration, verification (functional, timing, power, reliability), and layout (floorplanning, placement, routing). Lead semicustom memory methodology, apply AI/ML tools for RTL optimization and testbench generation, collaborate across CAD/EDA/architecture teams, and mentor peers.

The role involves designing and optimizing memory/logic/analog circuits, conducting simulations, and managing layout processes while collaborating with multiple teams to ensure product manufacturability.

Design and execute RTL verification for DRAM IP: define scope and strategy, build SV-UVM testbenches, run directed and constrained-random regressions, close functional/code coverage, debug RTL/testbench issues, and collaborate with designers. Maintain verification flows and tools, use scripting to automate regressions, and proactively adopt approved AI tools to improve verification productivity.

The Sr Engineer in Die Design Engineering will oversee TSV & 3D Integration, collaborate across teams, and ensure die design meets advanced packaging requirements.

The Staff Engineer will oversee verification activities for DRAM design, utilizing AI tools and simulation to enhance efficiency and provide support for design projects.

This role involves die design engineering focusing on TSV integration and advanced packaging, collaborating across teams and adopting new technologies while ensuring design reliability and innovation in HBM standards.

The Staff Engineer Design will engage in block and sub-system design, timing optimization, mentor junior designers, and collaborate on full-chip floorplanning while using various simulation tools.

Lead DFT strategy, integration, and optimization for NAND flash designs across digital, custom/analog, and array domains. Develop and validate test sequences, firmware, and simulations (Verilog/XA); support first-silicon bring-up, post-silicon validation, failure analysis, and high-volume ramp while collaborating with cross-functional teams.

The role involves owning functional verification for designs, developing tests, debugging failures, driving coverage closure, and leading junior engineers in verification methodologies.

Responsible for developing and integrating foundry rule decks, QA of PDKs, and automating verification processes using various programming languages.

The SR Engineer in Design Verification will simulate, analyze, and debug pre-silicon chip designs, develop test cases, and enhance verification methodologies for DRAM and emerging memory architectures.

Design and maintain standard cells for DRAM products; collaborate on architecture, perform characterization, and develop automation tools; enhance design using AI.

The Senior Principal Analog Design Engineer will lead the design and development of analog integrated circuits, mentoring others and overseeing the full lifecycle from concept to silicon validation in automotive and industrial applications.

The Sr. Principal Design Engineer at Cadence will lead SOC verification, develop test plans, and mentor engineers, ensuring high-quality execution of complex projects.

Design and develop RTL for high-performance SSD/NAND/DDR controllers, implement NVMe/PCIe/DDR/ONFI protocols, optimize performance/latency/power, and support verification, integration, and silicon debug. Drive automation and tooling; apply AI/ML and scripting for debug and performance analysis when applicable.

Design RTL for high-speed IO IPs (UFS/Ethernet/PCIe/USB) for automotive SoCs: define micro-architecture, implement RTL, drive verification, close timing, and support silicon validation while collaborating with architects and physical design teams.

The role involves RTL verification of memory technologies, guiding verification efforts, developing methodologies, and optimizing using AI tools. Requires collaboration on complex chip design projects.