Top Design Engineer Jobs in Hyderabad

The role involves designing and optimizing memory/logic/analog circuits, conducting simulations, and managing layout processes while collaborating with multiple teams to ensure product manufacturability.

Lead RTL-to-GDSII physical implementation for advanced SoCs, handling floorplanning, power planning, CTS, place-and-route, timing closure, and signoff (STA, SI, EM/IR, DRC/LVS). Optimize PPA and low-power implementation, drive methodology and automation, mentor teams, collaborate across architecture/RTL/DFT/verification/CAD, and adopt AI/Generative/Agentic tools to improve productivity. Custom layout experience for analog/mixed-signal integration is a plus.

Lead DFT strategy, integration, and optimization for NAND flash designs across digital, custom/analog, and array domains. Develop and validate test sequences, firmware, and simulations (Verilog/XA); support first-silicon bring-up, post-silicon validation, failure analysis, and high-volume ramp while collaborating with cross-functional teams.

Design digital IP blocks from microarchitecture to RTL and support physical hardware development. Lead SoC integration and verification (CDC, lint, synthesis, STA, power), oversee layout and floor-planning, apply AI/ML tools to accelerate RTL optimization and testbench generation, collaborate with CAD/EDA/software and cross-functional teams, mentor engineers, and drive memory design methodology and future-generation innovations.

Design and validate on-chip controller and mixed-signal circuitry for NAND flash. Responsibilities include architecture development, transistor-level design, RTL implementation, firmware for NAND operations, full-chip Verilog validation, test planning, system integration, and use of design/verification CAD tools. AI tools encouraged to automate workflows.

The Memory Circuit Design Engineer will design and optimize memory circuits, manage layout processes, verify designs, and collaborate across teams to enhance product manufacturability.

Lead end-to-end ASIC IP, subsystem, and SoC development from micro-architecture through RTL integration, verification support, synthesis, timing, power analysis, and physical hardware collaboration. Define interfaces and architecture, support post-silicon debug and bring-up, collaborate with cross-functional global teams, improve workflows using AI-assisted engineering tools, and mentor engineers. The role focuses on memory and storage products, with preferred experience in LPDDR, CPU subsystems, test controllers, and storage or memory ASIC controllers.

Design digital IP blocks from microarchitecture to RTL, oversee physical development and verification processes, and mentor teams for DRAM technology innovation.

The Staff Engineer will work on ASIC physical design, focusing on low power design, timing closure, IR/EM analysis, and tape-out activities, requiring 8+ years of experience in the field.

Own verification and end-to-end analysis of advanced DRAM full-chip and block-level designs. Develop SystemVerilog/UVM testbenches, test cases, stimuli, regressions, and coverage improvements; debug pre-silicon designs and support silicon learning loops. Build verification methodologies and environments using digital, mixed-signal, SPICE, and AI-assisted automation tools. Collaborate globally, validate AI-generated outputs, guide team members, and contribute to DDR and emerging memory verification projects.

The role involves guiding verification efforts for memory designs, developing test cases, and collaborating internationally on verification methodologies and automation.

Supports DRAM and emerging-memory design verification through test-case development, testbench and test-vector maintenance, simulation, regression testing, functional coverage analysis, and pre-silicon debug. Uses AI-driven workflows and automation to accelerate verification and improve debugging. Collaborates internationally on verification methodologies and environments while applying SPICE, Verilog, gate-level analysis, and CMOS circuit knowledge.

The Design Engineer will assist in developing new product designs, manage the layout process, perform verification, and improve design quality.

Lead full-chip functional verification for non-volatile memory designs using SystemVerilog and UVM. Develop verification plans and testbenches, write assertions and coverage points, run constrained-random tests, debug with digital designers, close coverage to tape-out, and develop/support NAND Flash behavioral models while collaborating with application engineers.

Lead end-to-end RTL design and integration for complex SoC, subsystem, and IP blocks. Define micro-architecture, develop Verilog/SystemVerilog RTL, and drive design closure across verification, physical design, DFT, firmware, and architecture teams. Address timing, power, area, clocking, reset, lint, CDC, RDC, synthesis, formal, and low-power requirements. Debug simulation, emulation, silicon, and customer issues; review specifications and designs; mentor engineers; and improve reusable IP and design methodologies.

Responsible for verification of DRAM critical timings, guiding verification efforts, analyzing full chip designs, and developing verification methodologies.

The role involves the verification and analysis of memory circuit designs, guiding verification efforts, and developing testing methodologies collaboratively. Candidates should possess skills in circuit analysis, simulation, and scripting.

Lead end-to-end verification for advanced memory circuit designs, including full-chip gate-level simulations, testbench and test-vector development, regression execution, functional coverage analysis, and debugging. Guide verification strategy, develop methodologies and environments, support DRAM and emerging memory architectures, and collaborate with global design teams. Mentor team members and help develop AI-based automation, AMS verification, and co-simulation capabilities.

Design and maintain standard cells for DRAM products, collaborate on architecture, characterize models, develop automation tools, and enhance productivity using AI.

Lead end-to-end IP and SoC development from micro-architecture through reusable RTL design, integration, and post-silicon bring-up. Drive CDC, lint, synthesis/STA, and power analysis; define module interfaces and system-level architecture. Collaborate with Verification, FW, DFT, Synthesis, and Physical Design teams, mentor engineers, and apply AI-enabled workflows per Micron governance to improve productivity and automation.

The Senior Engineer will design and validate on-chip controllers and mixed signal circuitry in NAND FLASH chips, performing RTL design, firmware coding, and full-chip verification.

The Principal Engineer will lead NAND Flash Memory design, manage chip verification processes, and collaborate across multiple engineering domains.

The Software Design Engineer will develop software solutions while collaborating with various engineering teams, integrating hardware and software, and optimizing products for consumer use.

Responsible for designing and developing software solutions, BSP integration, code optimizations, and debugging hardware/firmware interactions.

Develop software solutions for Surface devices, collaborating with engineers and optimizing product designs for high-volume consumer products.