Top Design Engineer Jobs in Hyderabad

Develop new memory products by designing DRAM Memory arrays and circuits, optimizing layouts, and leveraging AI tools for design processes.

The Senior Physical Design Engineer will manage physical implementation tasks for SoC designs, including floorplanning, timing closure, and signoff activities. They will work on digital blocks and collaborate with various teams to resolve implementation challenges while ensuring design integrity and efficiency.

The role involves designing and optimizing memory/logic/analog circuits, conducting simulations, and managing layout processes while collaborating with multiple teams to ensure product manufacturability.

This role involves block-level and sub-system design, timing optimization, circuit optimization, mentoring juniors, and documenting Micro-Architecture Specifications.

The Memory Circuit Design Engineer will design and optimize memory circuits, manage layout processes, verify designs, and collaborate across teams to enhance product manufacturability.

The Memory Circuit Design Engineer will design, layout, and optimize memory circuits, manage layout processes, validate designs, and collaborate across teams to enhance product manufacturability and design quality.

Responsible for logic design of on-chip memory controllers, project management, verification processes, and team mentoring at Micron Technology.

The role involves block and sub-system design, timing optimization, critical circuit design, mentoring junior engineers, and documenting specifications according to industry standards.

The role requires designing and validating analog and mixed-signal circuits for NAND Flash technology, involving extensive lifecycle responsibilities and coordination with multi-functional teams.

Guide verification efforts, develop test cases for DRAM memory designs, maintain test benches, and leverage AI tools for automation in verification cycles.

The Senior Engineer will develop and maintain verification testbenches, simulate block-level RTL, and identify verification gaps while collaborating with design projects in DRAM.

The Principal DRAM Power Integrity Engineer develops methodologies for EMIR analysis, collaborates across teams, and maintains EMIR analysis tools and dashboards.

The role involves RTL verification of memory technologies, guiding verification efforts, developing methodologies, and optimizing using AI tools. Requires collaboration on complex chip design projects.

The Engineer will develop and standardize methodologies for EMIR analysis, perform electrical analysis, collaborate with design teams, leverage AI tools, and maintain dashboards for tracking results across DRAM products.

The Staff Engineer will focus on RTL design, SoC integration, and collaborate with cross-functional teams while leveraging AI skills.

The Design Verification Engineer will own functional verification, develop test plans, create SystemVerilog testbenches, run simulations, and mentor junior engineers while improving verification methodologies.

The IO Mixed Signal Design Engineer will integrate and verify mixed signal blocks in FPGA's, develop analog circuits for IO applications, work with design requirements, optimize circuits, and support post-tapeout phase.

The Principal IO Mixed Signal Design Engineer will integrate and verify mixed signal blocks in high-speed IOs for FPGAs, develop custom circuits, and support post-tapeout phases.

The Sr Engineer in Die Design Engineering will oversee TSV & 3D Integration, collaborate across teams, and ensure die design meets advanced packaging requirements.

Oversee verification of custom memory circuit designs, simulate and debug pre-silicon full chip designs, and develop test cases to ensure functionality and correct performance of DRAM and emerging memory architectures.

Support electrical design and documentation by executing new designs, creating performance curves, and managing engineering changes while collaborating with global stakeholders.

Lead physical design activities for GPUs and ASICs, focusing on design implementation, troubleshooting, and process improvements. Collaborate with teams to address design challenges and improve RTL2GDS flow.

The Principal Engineer will drive ASIC SoC design and development, focusing on IP, micro-architecture, RTL design, and end-to-end SoC execution, collaborating with global teams.

The Staff Verification Design Engineer will perform RT-level verification, run simulations, develop tests, and support post-silicon debugging while collaborating with design teams.

As a Senior Design Verification Engineer, you will develop verification plans, build TestBenches, and ensure functional coverage for non-volatile memory designs.