Top Design Engineer Jobs in Hyderabad

Designs and integrates digital IP and full-chip DRAM RTL from microarchitecture through verification and physical development. Responsibilities include architecture and interface definition, CDC, lint, synthesis, timing and power analysis, layout oversight, and functional, reliability, and silicon validation. The engineer will apply AI-assisted design and verification workflows, collaborate across architecture, CAD, EDA, software, verification, and physical design teams, mentor engineers, and advance memory design methodologies.

Designs, lays out, models, simulates, verifies, and optimizes memory, logic, and analog circuits. Responsibilities include parasitic modeling, floor-planning, routing, design validation, reticle experiments, tape-out revisions, and manufacturability coordination. Collaborates with CAD, modeling, verification, process integration, product engineering, manufacturing, and test teams to standardize workflows and advance future memory generations. The role also encourages AI-based tools and automation to improve design efficiency.

Designs and optimizes memory, logic, and analog circuits for DRAM and emerging memory products. Performs simulation, verification, layout, reliability analysis, tape-out revisions, and manufacturability reviews. Collaborates with cross-functional engineering, manufacturing, testing, process, and marketing teams. Leads junior engineers and technical experts while driving design standardization, innovation, automation, and use of AI-based tools.

Design and deliver RTL for complex DRAM, memory, and mixed-signal digital blocks. Own front-end ASIC development from architecture through RTL implementation, verification support, synthesis, timing closure, and implementation handoff. Define timing and power constraints, analyze performance and PPA, collaborate across architecture, verification, circuit, and physical design teams, improve RTL-to-GDS methodologies, and mentor peers. The role requires advanced Verilog/SystemVerilog expertise and extensive ASIC or SoC design experience.

Leads architecture, design, verification, integration, silicon validation, and production qualification of complex analog and mixed-signal circuits for advanced DRAM products. Drives IP development from concept through tape-out and manufacturing, optimizing power, performance, area, reliability, yield, and manufacturability. Provides technical leadership, mentors engineers, advances reusable IP and patents, and collaborates across product, process, test, assembly, and manufacturing teams.

Design and enable ASIC, memory, SoC, mixed-signal, and semiconductor CAD flows. Develop automation using scripting and programming languages, integrate EDA and AI-assisted tools, and lead physical implementation, timing closure, DFT, custom layout, verification, and signoff. Collaborate across engineering teams to support tape-out, manufacturability, silicon success, production ramp, documentation, training, and methodology improvements.

Designs and optimizes NAND core circuits, including row drivers, column drivers, sense amplifiers, and control circuitry. Leads circuit analysis, timing optimization, verification, layout supervision, full-chip integration, and analog/mixed-signal architecture development. Collaborates with RTL, technology, and project teams on Flash functionality, floorplanning, operating conditions, and waveforms. Uses simulation, scripting, automation, and AI-enabled methodologies to improve productivity. Mentors junior engineers and maintains design specifications and quality documentation.

Leads end-to-end ASIC IP, subsystem, and SoC development from micro-architecture through RTL integration and physical design support. Responsibilities include CDC, lint, synthesis, timing, power analysis, architecture reviews, cross-functional collaboration, post-silicon debug, and technical mentorship. The role also applies approved AI tools to improve SoC design workflows and engineering productivity.

Leads end-to-end ASIC IP, subsystem, and SoC development from micro-architecture through RTL design, integration, synthesis, timing, power analysis, and physical hardware support. Collaborates with architecture, verification, firmware, DFT, synthesis, and physical design teams. Supports post-silicon debug, silicon bring-up, methodology reviews, and technical mentorship while applying AI-enabled engineering workflows.

Leads end-to-end ASIC IP, subsystem, and SoC development from micro-architecture through RTL design, integration, synthesis, timing, power analysis, and physical hardware support. Defines architectures and interfaces, collaborates with verification, firmware, DFT, synthesis, and physical design teams, and supports post-silicon debug. The role also provides technical mentorship, drives methodology reviews, and applies approved AI-enabled engineering workflows.

Design and own RTL development for an AI-enabled RISC-V CPU core, including microarchitecture, vector/matrix engines, performance/power/area optimization, and verification support. Collaborate with cross-functional teams for timing, reliability, testability, and SoC integration.

Develop verification components and simulation environments for complex ASIC and SoC designs. Define and execute block, subsystem, and top-level test plans; apply constrained-random verification, functional coverage, and UVM-based SystemVerilog testbenches. Debug complex issues, collaborate with design teams, track verification quality metrics, and support timely delivery of high-quality PCIe IP and subsystem verification.

Designs RTL for BOOT and power-management subsystems in automotive and client chips. Responsibilities include architectural trade-offs, micro-architecture development, RTL implementation, verification leadership, timing closure, physical-design collaboration, and silicon validation. The role requires strong digital design and verification fundamentals, subsystem design experience, analytical problem-solving, and collaboration across global engineering teams.

As a Graduate Design Engineer, you will design telecommunication structures, prepare documentation, manage design risks, and create CAD drafts.

Lead physical design implementation and integration from block to full-chip level, covering floorplanning, synthesis, placement, CTS, routing, static timing, physical verification, formal equivalence, power/IR-drop and EM analysis. Drive flow development/automation, evaluate technology/IP/vendors, support tapeouts in leading-edge nodes, report status/risks, and collaborate with program teams. Occasional travel may be required.

Leads end-to-end verification for complex DRAM IP and subsystems, defining strategy, developing SystemVerilog/UVM testbenches, running constrained-random regressions, analyzing failures, and closing coverage metrics. Provides technical leadership across distributed teams, mentors engineers, drives methodology roadmaps, debugs RTL and verification environments, communicates project risks, and supports tapeout readiness for advanced low-power memory designs.

Leads physical design planning, top-level integration, and block-level APR for memory and logic products. Responsibilities include floorplanning, placement, routing, timing closure, DRC/LVS/EM-IR signoff, ECO convergence, constraint development, parasitic modeling, and design validation. Automates flows using Tcl, SKILL, and Python, improves methodology with AI, and collaborates with STA, DFT, CAD, custom-layout, manufacturing, and product engineering teams.

Design complex, high-density, high-speed analog, digital, RF, and mixed-signal PCBs for server-class and HDI platforms. Create libraries and footprints, establish electrical constraints, route high-speed interfaces, design power supplies, and address power integrity, thermal, and reliability requirements. Generate and validate manufacturing data, manage PCB-to-mechanical conversions, and support release processes. Collaborate with signal and power integrity, mechanical, manufacturing, DFM/DFA, and CAD teams using major PCB design tools.

Designs and debugs analog circuits, including SerDes components, while meeting PPA and performance goals. Collaborates with layout teams to resolve design issues, generates sign-off design views, completes QA checks, prepares design reviews, and closes action items. Requires strong AMS design-flow fundamentals, familiarity with SPICE simulation tools, schedule ownership, quality delivery, and client communication. The role requires 3–10 years of experience and a bachelor’s degree in engineering, with a master’s preferred.

Design and integrate RTL for complex ASIC and SoC projects using Verilog/SystemVerilog. Develop multi-clock and asynchronous interfaces, apply lint and CDC analysis, support synthesis and timing analysis, execute ECO fixes, and perform formal verification. The role requires knowledge of AMBA AXI, AHB, and APB protocols, as well as SoC clocking and reset architectures. Strong communication, collaboration, curiosity, and a proactive approach are expected.

Supports mechanical design and engineering requisition activities for motor products, including modeling, drafting, bills of materials, sampling, new model releases, engineering changes, and documentation. Partners with engineers and application teams across global manufacturing sites, supports cost reduction and simplification projects, develops basic test plans, and drives continuous improvement while maintaining accuracy and customer responsiveness.

Leads a digital IP design team and oversees architecture, RTL development, verification quality, timing closure, DFT, low-power design, and silicon debug. Designs configurable digital blocks and integrates processor subsystems, interfaces, peripherals, and protocols. Manages IP curation, third-party IP evaluation, design workflows, quality metrics, stakeholder communications, schedules, and delivery. Provides technical mentorship, drives process improvements, and develops reusable IP infrastructure across business units.

Performs block and chip-level RTL verification for DRAM and emerging memory designs. Develops SV-UVM testbenches, test vectors, directed and constrained-random tests, and regression suites. Analyzes failures, debugs RTL and verification environments, closes functional and code coverage, identifies verification gaps, and supports tapeout readiness. Collaborates with design and international engineering teams, communicates risks and status, and uses scripting and approved AI tools to improve verification workflows.

Owns RTL architecture and design for on-chip memory controllers and complex memory-product blocks. Responsibilities include meeting performance, power, and area targets; developing synthesis and timing constraints; performing verification, timing closure, physical signoff, and ECOs; supporting post-layout simulation, silicon validation, and tape-out. The role also establishes design practices, mentors and trains engineers, participates in recruiting, collaborates across engineering teams, and applies AI to design and verification automation.

Design and validate high-speed analog, digital, and mixed-signal CMOS circuits for non-volatile memory datapaths and DDR interfaces. Responsibilities include circuit and timing optimization, layout supervision, full-chip integration, AMS simulation, signal integrity and reliability validation, microarchitecture documentation, and collaboration across application, modeling, technology, reliability, and product teams. The role also promotes AI-enabled design and validation methodologies and requires technical leadership in advanced semiconductor processes.