Top Design Engineer Jobs in Hyderabad

The role involves designing and optimizing memory/logic/analog circuits, conducting simulations, and managing layout processes while collaborating with multiple teams to ensure product manufacturability.

Design and optimize memory, logic, and analog circuits; perform parasitic modeling, layout (floor-planning, placement, routing), and verification using industry-standard simulators; collaborate cross-functionally to ensure manufacturability and drive future memory generation innovation.

The Analog Design Engineer will design and optimize circuits for advanced DRAM products, manage layout, perform verification, and contribute to cross-group communications.

Design and optimize DRAM memory arrays, peripheral logic, and analog circuits. Drive layout, floor-planning, placement, routing, and circuit-level verification. Integrate AI-driven flows and collaborate with CAD/EDA teams to improve simulation, parasitics, and design sign-off for future memory generations.

The Senior Memory Circuit Design Engineer will manage the memory design process, perform simulations, and ensure manufacturability while collaborating across teams.

The Memory Circuit Design Engineer will design and optimize memory circuits, manage layout processes, verify designs, and collaborate across teams to enhance product manufacturability.

Design digital IP blocks from microarchitecture to RTL, oversee physical development and verification processes, and mentor teams for DRAM technology innovation.

The Memory Circuit Design Engineer will design, layout, and optimize memory circuits, manage layout processes, validate designs, and collaborate across teams to enhance product manufacturability and design quality.

The Design Engineer will assist in developing new product designs, manage the layout process, perform verification, and improve design quality.

Design digital IP blocks, drive full-chip integration, collaborate on AI-driven design processes, and mentor teams in advanced memory design.

The Senior Physical Design Engineer is responsible for executing physical design implementation for SoC blocks, driving timing closure, performing verification checks, supporting tape-out activities, and mentoring junior engineers.

The Senior Engineer will design and maintain standard cells for DRAM products, collaborate on architecture development, and perform characterization and quality analysis of cells. Development of automation tools and engagement in AI-assisted design improvements are also key responsibilities.

The Staff Engineer Design role involves block level and full-chip design, timing optimization, circuit optimization, and mentoring junior engineers in semiconductor design, particularly focusing on Flash technology and CMOS physics.

The Engineer, Design role involves full-chip functional verification of memory designs, developing verification plans, TestBench development in SystemVerilog, and collaborating with teams to debug and enhance memory functionalities.

The role involves defining verification scope, developing testbenches, executing tests, debugging RTL, and collaborating on verification methods for DRAM technology.

Responsible for logic design of on-chip memory controllers, project management, verification processes, and team mentoring at Micron Technology.

The Scribe Design Engineer will design, layout, and verify CMOS test structures, collaborate with global teams, and manage projects to improve performance.

Design and implement semicustom digital blocks (control logic, BIST, DfT); drive RTL-to-GDS flows including synthesis, CTS, P&R and timing closure; perform functional and gate-level verification; develop testbenches and scripting; support silicon bring-up, post-silicon validation, and continuous improvement of semicustom design flows.

The Senior Engineer will oversee verification activities for DRAM design, leveraging AI tools, developing test cases, and improving debug efficiency in digital/mixed signal verification.

The Principal Engineer will drive ASIC SoC design and development, focusing on IP, micro-architecture, RTL design, and end-to-end SoC execution, collaborating with global teams.

Responsible for the design, layout, and verification of CMOS electrical test structures, improve automation flows, and mentor junior team members.

The role involves guiding verification efforts for memory designs, developing test cases, and collaborating internationally on verification methodologies and automation.

The Principal Engineer will lead NAND Flash Memory design, manage chip verification processes, and collaborate across multiple engineering domains.

Design and produce railway track alignment designs, switches/crossovers, platform and track bed designs; produce calculations, models, drawings and reports; use rail CAD tools; document in CDE/BIM; support senior engineers and mentor graduates.

Design and produce track alignment designs, including switches, crossovers, platforms, track bed and gauging analysis. Create models, drawings, calculations, reports and BIM-compliant deliverables using rail design software. Coordinate with senior engineers, support graduates, and follow regulations, quality plans and industry standards throughout project delivery.