Top Design Engineer Jobs in Hyderabad

Leads architecture, design, verification, integration, silicon validation, and production qualification of complex analog and mixed-signal circuits for advanced DRAM products. Drives IP development from concept through tape-out and manufacturing, optimizing power, performance, area, reliability, yield, and manufacturability. Provides technical leadership, mentors engineers, advances reusable IP and patents, and collaborates across product, process, test, assembly, and manufacturing teams.

Design and enable ASIC, memory, SoC, mixed-signal, and semiconductor CAD flows. Develop automation using scripting and programming languages, integrate EDA and AI-assisted tools, and lead physical implementation, timing closure, DFT, custom layout, verification, and signoff. Collaborate across engineering teams to support tape-out, manufacturability, silicon success, production ramp, documentation, training, and methodology improvements.

Design and deliver RTL for complex DRAM, memory, and mixed-signal digital blocks. Own front-end ASIC development from architecture through RTL implementation, verification support, synthesis, timing closure, and implementation handoff. Define timing and power constraints, analyze performance and PPA, collaborate across architecture, verification, circuit, and physical design teams, improve RTL-to-GDS methodologies, and mentor peers. The role requires advanced Verilog/SystemVerilog expertise and extensive ASIC or SoC design experience.

Designs, lays out, models, simulates, verifies, and optimizes memory, logic, and analog circuits. Responsibilities include parasitic modeling, floor-planning, routing, design validation, reticle experiments, tape-out revisions, and manufacturability coordination. Collaborates with CAD, modeling, verification, process integration, product engineering, manufacturing, and test teams to standardize workflows and advance future memory generations. The role also encourages AI-based tools and automation to improve design efficiency.

Own verification and end-to-end analysis of full-chip gate-level DRAM designs. Develop SystemVerilog and UVM testbenches, test cases, stimuli, test vectors, regressions, and coverage improvements. Simulate, debug, and analyze pre-silicon block and full-chip designs using digital, mixed-signal, and SPICE tools. Apply AI-based automation to accelerate verification while validating outputs against specifications, simulations, waveforms, assertions, and coverage. Guide newer engineers and collaborate globally on verification methodologies and environments.

The Staff Engineer Design role involves block level and full-chip design, timing optimization, circuit optimization, and mentoring junior engineers in semiconductor design, particularly focusing on Flash technology and CMOS physics.

Design and maintain standard cells for DRAM products, collaborate on architecture, characterize models, develop automation tools, and enhance productivity using AI.

The Staff Engineer Design will engage in block and sub-system design, timing optimization, mentor junior designers, and collaborate on full-chip floorplanning while using various simulation tools.

The Senior Engineer will design and maintain standard cells for DRAM products, collaborate on architecture development, and perform characterization and quality analysis of cells. Development of automation tools and engagement in AI-assisted design improvements are also key responsibilities.

Leads end-to-end ASIC and SoC development, including microarchitecture, RTL design, IP and subsystem integration, CDC, lint, synthesis, timing, and power analysis. Collaborates with architecture, verification, firmware, DFT, and physical design teams; supports post-silicon debug and bring-up; reviews methodologies and mentors engineers. Applies approved AI tools to improve design analysis, coding, documentation, automation, and workflow quality.

Develop and support embedded and interface software for semiconductor manufacturing equipment. Work across bare-metal and Linux environments using C, C++, and Python to interface with custom hardware and microcontrollers. Collaborate with software, electrical, controls, and mechanical engineers on equipment design, PCB and schematic review, circuit prototyping, debugging, testing, documentation, and system integration. Support existing equipment and use laboratory instruments for design bring-up and characterization.

Support DRAM design verification by developing test cases, test benches, test vectors, and verification environments. Simulate, analyze, and debug pre-silicon block-level and full-chip designs; run regressions and improve functional coverage. Use AI-based tools, agentic workflows, and automation to accelerate verification and debugging. Collaborate internationally on verification methodologies for DRAM and emerging memory products.

The Principal Engineer will lead NAND Flash Memory design, manage chip verification processes, and collaborate across multiple engineering domains.

Leads physical design planning, top-level integration, and block-level APR for memory and logic products. Responsibilities include floorplanning, placement, routing, timing closure, DRC/LVS/EM-IR signoff, ECO convergence, constraint development, parasitic modeling, and design validation. Automates flows using Tcl, SKILL, and Python, improves methodology with AI, and collaborates with STA, DFT, CAD, custom-layout, manufacturing, and product engineering teams.

Design railway signalling systems, including trackside equipment, interlockings, train control systems, and communication interfaces. Produce CAD drawings, ensure compliance with railway safety standards, conduct design reviews and hazard assessments, maintain technical documentation, and support procurement, installation, testing, commissioning, audits, and certification. Collaborate with systems engineers, project managers, regulatory authorities, and other stakeholders while contributing to safe and reliable rail infrastructure.

Design and optimize railway Overhead Line Equipment and SCADA systems for AC and DC traction networks. Responsibilities include system architecture, technical specifications, calculations, simulations, load-flow studies, standards compliance, site assessments, tender support, vendor coordination, and technical assistance during construction and commissioning. The role collaborates across engineering disciplines and supports metro, high-speed rail, and urban electrification projects.

Leads end-to-end railway signalling design for large infrastructure projects, including interlocking logic, ATS architecture, wayside layouts, control tables, and system interfaces. Reviews vendor documentation, supports installation, testing, commissioning, hazard analyses, and safety assessments. Ensures compliance with railway standards and certification requirements, collaborates with multidisciplinary teams, manages technical documentation, and mentors junior engineers.

Design and deliver integrated telecommunications systems for railway and metro infrastructure, including PA, IP networks, CCTV, fiber optics, radio communications, and network management systems. Prepare technical drawings, specifications, BOMs, and integration plans; coordinate with multidisciplinary teams; support installation, testing, commissioning, troubleshooting, and compliance activities. Maintain project documentation and participate in design reviews, client presentations, and technical evaluations.

Develops and improves physical design methodologies and RTL2GDSII flows for NVIDIA GPUs and SoCs. Responsibilities include floorplanning, placement and routing, clock tree synthesis, timing closure, physical verification, RC extraction, EMIR analysis, and DRC. The engineer builds automation scripts, supports EDA tools and tapeouts, resolves design issues, and improves power, performance, and area across chip designs.

Lead verification architecture and methodology for next-generation DDR memory designs. Develop UVM-based testbenches, verification plans, coverage strategies, and sign-off criteria. Integrate AMS co-simulation and AI/ML-assisted tools for regression, failure classification, and predictive analysis. Mentor verification engineers, collaborate with build teams and EDA vendors, and drive automation and debugging efficiency.

The Principal DRAM Power Integrity Engineer develops methodologies for EMIR analysis, collaborates across teams, and maintains EMIR analysis tools and dashboards.

Leads silicon design validation for NAND Flash products, including development, simulation, bench testing, characterization, qualification, and silicon debugging. Heads technical task forces, drives issue resolution, performs wafer and tester measurements, and collaborates with R&D, design, manufacturing, business, and quality teams. The role requires strong analog and mixed-signal VLSI expertise, memory architecture knowledge, data analysis, and programming or scripting capabilities.

Design and optimize DRAM memory arrays, peripheral logic, and analog circuits. Lead layout floor-planning, placement, routing, circuit-level verification, timing, power, reliability, parasitic, and silicon analysis. Develop semicustom memory methodologies and integrate AI-driven automation into simulation, verification, and sign-off flows. Collaborate with CAD, EDA, and software teams while driving innovation for future memory generations.

Design, implement, simulate, and validate analog and mixed-signal circuits for NAND Flash across the full design lifecycle. Responsibilities include transistor-level optimization, silicon issue analysis, cross-functional collaboration, technical coordination, and development of AI-assisted engineering workflows for simulation, verification, automation, and documentation.

Leads ASIC physical design implementation for processors, controllers, and enterprise SSD architectures. Responsibilities include floorplanning, placement, clock-tree synthesis, routing, extraction, timing closure, IR/EM analysis, physical verification, PPA optimization, and tapeout. The role requires advanced-node experience, tool expertise, independent subsystem leadership, AI-assisted closure skills, and strong collaboration and analytical abilities.