Top Design Engineer Jobs in Hyderabad

The role involves designing and optimizing memory/logic/analog circuits, conducting simulations, and managing layout processes while collaborating with multiple teams to ensure product manufacturability.

Design digital IP blocks, drive full-chip integration, collaborate on AI-driven design processes, and mentor teams in advanced memory design.

Develop new memory products by designing DRAM Memory arrays and circuits, optimizing layouts, and leveraging AI tools for design processes.

The Senior Memory Circuit Design Engineer will manage the memory design process, perform simulations, and ensure manufacturability while collaborating across teams.

The role involves block and sub-system design, timing optimization, critical circuit design, mentoring junior engineers, and documenting specifications according to industry standards.

Responsible for logic design of on-chip memory controllers, project management, verification processes, and team mentoring at Micron Technology.

The Senior Physical Design Engineer will manage physical implementation tasks for SoC designs, including floorplanning, timing closure, and signoff activities. They will work on digital blocks and collaborate with various teams to resolve implementation challenges while ensuring design integrity and efficiency.

The Analog Design Engineer will design and optimize circuits for advanced DRAM products, manage layout, perform verification, and contribute to cross-group communications.

The Memory Circuit Design Engineer will design and optimize memory circuits, manage layout processes, verify designs, and collaborate across teams to enhance product manufacturability.

The Memory Circuit Design Engineer will design, validate, and optimize memory circuits, oversee layout processes, and improve design efficiency through collaboration and AI tools.

Design digital IP blocks from microarchitecture to RTL, oversee physical development and verification processes, and mentor teams for DRAM technology innovation.

This role involves block-level and sub-system design, timing optimization, circuit optimization, mentoring juniors, and documenting Micro-Architecture Specifications.

The role involves RTL verification of memory technologies, guiding verification efforts, developing methodologies, and optimizing using AI tools. Requires collaboration on complex chip design projects.

The Principal DRAM Power Integrity Engineer develops methodologies for EMIR analysis, collaborates across teams, and maintains EMIR analysis tools and dashboards.

The Senior Engineer will focus on full-chip functional verification of non-volatile memory designs, developing verification plans, TestBench development, and collaborating with the digital design team for accurate designs.

The Memory Circuit Design Engineer will design, layout, and optimize memory circuits, manage layout processes, validate designs, and collaborate across teams to enhance product manufacturability and design quality.

The role involves auditing verification plans, engaging in post-silicon learning activities, and leveraging AI tools for workflow enhancement.

The Design Engineer will assist in developing new product designs, manage the layout process, perform verification, and improve design quality.

The Engineer will develop and standardize methodologies for EMIR analysis, perform electrical analysis, collaborate with design teams, leverage AI tools, and maintain dashboards for tracking results across DRAM products.

The Sr Engineer in Die Design Engineering will oversee TSV & 3D Integration, collaborate across teams, and ensure die design meets advanced packaging requirements.

The role focuses on developing verification components for SOC designs, executing verification plans, debugging, and ensuring quality delivery. Requires expertise in NAND, DDR, PCIe, and UVM-based test benches.

The Principal Engineer will drive ASIC SoC design and development, focusing on IP, micro-architecture, RTL design, and end-to-end SoC execution, collaborating with global teams.

This role involves die design engineering focusing on TSV integration and advanced packaging, collaborating across teams and adopting new technologies while ensuring design reliability and innovation in HBM standards.

The Principal Engineer, Design leads the development and design of NAND Flash Memory, innovating features, ensuring manufacturability, and overseeing full chip verification and cross-functional collaboration.

The Design Verification Engineer will own functional verification, develop test plans, create SystemVerilog testbenches, run simulations, and mentor junior engineers while improving verification methodologies.