Top Design Engineer Jobs in Hyderabad

Designs and optimizes memory, logic, and analog circuits for DRAM and emerging memory products. Performs simulation, verification, layout, reliability analysis, tape-out revisions, and manufacturability reviews. Collaborates with cross-functional engineering, manufacturing, testing, process, and marketing teams. Leads junior engineers and technical experts while driving design standardization, innovation, automation, and use of AI-based tools.

Design and optimize DRAM memory arrays, peripheral logic, and analog circuits. Lead layout floor-planning, placement, routing, circuit-level verification, timing, power, reliability, parasitic, and silicon analysis. Develop semicustom memory methodologies and integrate AI-driven automation into simulation, verification, and sign-off flows. Collaborate with CAD, EDA, and software teams while driving innovation for future memory generations.

Design and optimize DRAM memory arrays, peripheral logic, and analog circuits. Lead semicustom memory design methodology, layout, floor-planning, routing, circuit verification, parasitic analysis, and reliability studies. Apply AI-assisted tools and automation to improve schematic optimization, simulation, verification, and silicon-learning workflows. Collaborate with CAD, EDA, and software teams to integrate AI-driven design flows and advance future memory generations.

Designs and optimizes DRAM memory arrays, peripheral logic, and analog circuits. Responsibilities include schematic optimization, layout, floor-planning, placement, routing, circuit-level verification, parasitic analysis, timing, power and reliability assessment, and semiconductor design sign-off. The role develops semicustom memory methodologies and integrates AI-driven automation into simulation and verification workflows while collaborating with CAD, EDA, and software teams to advance future memory generations.

The role involves designing and optimizing memory/logic/analog circuits, conducting simulations, and managing layout processes while collaborating with multiple teams to ensure product manufacturability.

Designs and improves PCB load boards used with automated test equipment for semiconductor memory manufacturing. Responsibilities include circuit design and simulation, schematic capture, PCB development, testing, debugging, signal integrity analysis, lab measurements, Python scripting, documentation, engineering change control, prototype qualification, and customer issue resolution. The role works with global engineering, manufacturing, procurement, and contract manufacturing teams while applying AI-assisted tools and continuous improvement practices.

Lead RTL-to-GDSII physical implementation for advanced SoCs, handling floorplanning, power planning, CTS, place-and-route, timing closure, and signoff (STA, SI, EM/IR, DRC/LVS). Optimize PPA and low-power implementation, drive methodology and automation, mentor teams, collaborate across architecture/RTL/DFT/verification/CAD, and adopt AI/Generative/Agentic tools to improve productivity. Custom layout experience for analog/mixed-signal integration is a plus.

Lead DFT strategy, integration, and optimization for NAND flash designs across digital, custom/analog, and array domains. Develop and validate test sequences, firmware, and simulations (Verilog/XA); support first-silicon bring-up, post-silicon validation, failure analysis, and high-volume ramp while collaborating with cross-functional teams.

This role involves die design engineering focusing on TSV integration and advanced packaging, collaborating across teams and adopting new technologies while ensuring design reliability and innovation in HBM standards.

Own verification and end-to-end analysis of full-chip gate-level DRAM designs. Develop SystemVerilog and UVM testbenches, test cases, stimuli, test vectors, regressions, and coverage improvements. Simulate, debug, and analyze pre-silicon block and full-chip designs using digital, mixed-signal, and SPICE tools. Apply AI-based automation to accelerate verification while validating outputs against specifications, simulations, waveforms, assertions, and coverage. Guide newer engineers and collaborate globally on verification methodologies and environments.

Design digital IP blocks from microarchitecture to RTL and support physical hardware development. Lead SoC integration and verification (CDC, lint, synthesis, STA, power), oversee layout and floor-planning, apply AI/ML tools to accelerate RTL optimization and testbench generation, collaborate with CAD/EDA/software and cross-functional teams, mentor engineers, and drive memory design methodology and future-generation innovations.

Lead physical design implementation and integration at block/subsystem/sub-chip/SoC levels including floorplanning, synthesis, placement, CTS, routing, STA, physical verification, formal equivalency, power integrity (IR-drop/EM) and tapeout readiness. Drive PD flow automation, team delivery against milestones, vendor/IP evaluations, and report progress, issues, and risks to management.

Design and validate on-chip controller and mixed-signal circuitry for NAND flash. Responsibilities include architecture development, transistor-level design, RTL implementation, firmware for NAND operations, full-chip Verilog validation, test planning, system integration, and use of design/verification CAD tools. AI tools encouraged to automate workflows.

Leads verification architecture and methodology for next-generation HBM designs. Develops verification plans, coverage strategies, sign-off criteria, UVM-based testbenches, reusable verification components, and formal verification approaches. Partners with design teams to ensure verification completeness, mentors engineers, drives technical direction, and improves workflows through automation and AI-enabled verification. Requires expertise in SystemVerilog, UVM, simulation, coverage, regression management, SoC architecture, and bus protocols.

Designs and optimizes complex analog power-management IP for advanced DRAM products, including references, regulators, charge pumps, amplifiers, and comparators. Responsibilities include circuit layout, parasitic modeling, simulation, verification, tape-out revisions, manufacturability coordination, and cross-functional collaboration across engineering and manufacturing groups. The role also supports innovation for future memory generations and leverages AI.

Leads verification architecture and methodology for next-generation HBM designs. Responsibilities include developing verification plans, coverage strategies, sign-off criteria, UVM-based testbenches, reusable components, and formal verification approaches. The role partners with build teams, drives verification completeness, manages simulation and regressions, mentors engineers, and influences technical direction. AI-enabled verification and automation using Python or TCL are also encouraged.

Lead end-to-end IP and SoC development from micro-architecture through reusable RTL design, integration, and post-silicon bring-up. Drive CDC, lint, synthesis/STA, and power analysis; define module interfaces and system-level architecture. Collaborate with Verification, FW, DFT, Synthesis, and Physical Design teams, mentor engineers, and apply AI-enabled workflows per Micron governance to improve productivity and automation.

Leads silicon design validation for NAND Flash products, including development, simulation, bench testing, characterization, qualification, and silicon debugging. Heads technical task forces, drives issue resolution, performs wafer and tester measurements, and collaborates with R&D, design, manufacturing, business, and quality teams. The role requires strong analog and mixed-signal VLSI expertise, memory architecture knowledge, data analysis, and programming or scripting capabilities.

Design and optimize DRAM memory arrays, peripheral logic, and analog circuits. Lead layout, floorplanning, placement, routing, and circuit-level verification. Integrate AI-driven design and automation with CAD/EDA tools, perform parasitic extraction and simulations, and drive methodology improvements for future memory generations.

Lead physical design implementation and integration from block to full-chip level, covering floorplanning, synthesis, placement, CTS, routing, static timing, physical verification, formal equivalence, power/IR-drop and EM analysis. Drive flow development/automation, evaluate technology/IP/vendors, support tapeouts in leading-edge nodes, report status/risks, and collaborate with program teams. Occasional travel may be required.

Designs and validates FPGA intellectual property using RTL design, logic simulation, compilation, timing closure, and hardware debugging. The role requires programming skills in languages such as C/C++, Perl, Tcl, or Python, plus experience with high-speed I/O protocols including PCIe, Ethernet, CPRI, and JESD204B/C. Responsibilities may also include hardware validation, soft IP packaging, example designs, and testbench development.

Lead physical design and implementation for complex AI NPU semiconductor designs, including synthesis, floorplanning, power planning, placement, clock tree synthesis, routing, timing closure, static timing analysis, and physical verification. Collaborate with design, verification, DFT, and power integrity teams; resolve timing, area, power, DRC, LVS, IR drop, and electromigration issues. Develop automation scripts, improve design methodologies, and document implementation results.

Own verification and end-to-end analysis of full-chip gate-level custom memory designs. Develop SystemVerilog and UVM testbenches, test cases, stimulus, test vectors, regressions, and coverage improvements for DRAM and emerging memory architectures. Simulate, debug, and analyze block-level and full-chip designs using digital, mixed-signal, and AMS co-simulation tools. Improve verification methodology through automation and AI-assisted workflows, validate AI outputs, collaborate globally, and mentor team members.

Design, implement, and optimize analog and power-management IPs (bandgaps, references, regulators, amplifiers) for advanced DRAM process nodes. Perform parasitic modeling, verification with industry simulators, oversee layout and tape-out activities, collaborate with cross-functional teams (test, process, product) to ensure manufacturability and drive future memory innovations.

Own verification and end-to-end analysis of advanced DRAM and emerging-memory designs. Develop SystemVerilog/UVM testbenches, test cases, stimuli, regressions, and coverage improvements for block- and full-chip designs. Simulate and debug digital, mixed-signal, and gate-level circuits using industry verification tools. Improve verification workflows through AI-based tools, automation, and scripting while validating AI outputs. Collaborate globally, develop verification methodology, support silicon learning, and mentor newer engineers.