Top Design Engineer Jobs in Hyderabad

Design and optimize memory, logic, and analog circuits for next-generation memory products. Perform parasitic modeling, verification and simulation, manage layout (floor-planning, placement, routing), collaborate across engineering, test, and product teams, and drive manufacturability and tape-out iterations while leveraging AI-based tools to improve design efficiency.

Design, layout, and optimize memory/logic/analog circuits; perform parasitic modeling, simulation and verification; manage floor-planning, placement, routing and tape-out validation; coordinate cross-functional manufacturability and drive memory-generation innovation while leveraging AI-based tools to improve workflow.

The Memory Circuit Design Engineer will design and optimize memory circuits, manage layout processes, verify designs, and collaborate across teams to enhance product manufacturability.

Design digital IP blocks from microarchitecture to RTL, oversee physical development and verification processes, and mentor teams for DRAM technology innovation.

The Design Engineer will assist in developing new product designs, manage the layout process, perform verification, and improve design quality.

Responsible for logic design of on-chip memory controllers, project management, verification processes, and team mentoring at Micron Technology.

The role involves designing and optimizing memory/logic/analog circuits, conducting simulations, and managing layout processes while collaborating with multiple teams to ensure product manufacturability.

The role involves guiding verification efforts for memory designs, developing test cases, and collaborating internationally on verification methodologies and automation.

The Principal Engineer will lead NAND Flash Memory design, manage chip verification processes, and collaborate across multiple engineering domains.

Design and optimize DRAM memory arrays, peripheral logic, and analog circuits. Drive layout, floor-planning, placement, routing, and circuit-level verification. Integrate AI-driven flows and collaborate with CAD/EDA teams to improve simulation, parasitics, and design sign-off for future memory generations.

Lead design and implementation of enterprise software solutions for clients, develop new features, troubleshoot production issues, manage deployments, mentor engineers, and coordinate cross-functional teams to meet delivery timelines and quality standards.

The Principal Engineer is responsible for designing, analyzing digital circuits for memory products, managing verification, guiding new hires, and ensuring manufacturability through collaboration.

Design and automate scribe test structures and layouts to support R&D and manufacturing integration. Develop and maintain EDA automation flows, PCELL-based device layouts, and DUT generation. Collaborate with process, mask, device, reliability, and characterization teams, validate documentation/parametrics, drive data-driven optimization, and mentor junior engineers.

The IO Mixed Signal Design Engineer will integrate and verify mixed signal blocks in FPGA's, develop analog circuits for IO applications, work with design requirements, optimize circuits, and support post-tapeout phase.

Develop and support verification activities for DRAM and emerging memory designs, leveraging automation and AI tools to improve efficiency and coverage. Collaborate with teams to integrate methodologies.

The Staff Engineer will oversee verification activities for DRAM design, utilizing AI tools and simulation to enhance efficiency and provide support for design projects.

The Senior Engineer will focus on full-chip functional verification of non-volatile memory designs, developing verification plans, TestBench development, and collaborating with the digital design team for accurate designs.

The Sr Engineer in Die Design Engineering will oversee TSV & 3D Integration, collaborate across teams, and ensure die design meets advanced packaging requirements.

Lead physical design implementation and integration at block/subsystem/sub-chip/SoC levels including floorplanning, synthesis, placement, CTS, routing, STA, physical verification, formal equivalency, power integrity (IR-drop/EM) and tapeout readiness. Drive PD flow automation, team delivery against milestones, vendor/IP evaluations, and report progress, issues, and risks to management.

Lead physical design implementation and integration from block to full-chip level, covering floorplanning, synthesis, placement, CTS, routing, static timing, physical verification, formal equivalence, power/IR-drop and EM analysis. Drive flow development/automation, evaluate technology/IP/vendors, support tapeouts in leading-edge nodes, report status/risks, and collaborate with program teams. Occasional travel may be required.

Lead board and IC package design for high-performance SoCs/MCUs from block level to product release. Drive teams, define specifications, perform SI/PI and power design, support SoC bring-up, and liaise with manufacturing for DFM/DFX and packaging delivery.

Develop and maintain EDA flows and automation for physical ASIC implementation. Optimize PPA for IP cores across advanced foundries, manage regression infrastructure, perform digital implementation with Cadence tools, and create scripts (Python/Tcl/AI) to reduce design turnaround and debug synthesis/LEC issues.

Responsible for developing and integrating foundry rule decks, QA of PDKs, and automating verification processes using various programming languages.

The Software Design Engineer will develop software solutions while collaborating with various engineering teams, integrating hardware and software, and optimizing products for consumer use.

The Senior Principal Analog Design Engineer will lead the design and development of analog integrated circuits, mentoring others and overseeing the full lifecycle from concept to silicon validation in automotive and industrial applications.