Top Design Engineer Jobs in Hyderabad

The Senior Physical Design Engineer is responsible for executing physical design implementation for SoC blocks, driving timing closure, performing verification checks, supporting tape-out activities, and mentoring junior engineers.

The role involves block and sub-system design, timing optimization, critical circuit design, mentoring junior engineers, and documenting specifications according to industry standards.

Responsible for logic design of on-chip memory controllers, project management, verification processes, and team mentoring at Micron Technology.

The Analog Design Engineer will design and optimize circuits for advanced DRAM products, manage layout, perform verification, and contribute to cross-group communications.

The Memory Circuit Design Engineer will design, validate, and optimize memory circuits, oversee layout processes, and improve design efficiency through collaboration and AI tools.

Design digital IP blocks from microarchitecture to RTL, oversee physical development and verification processes, and mentor teams for DRAM technology innovation.

The Memory Circuit Design Engineer will design and optimize memory circuits, manage layout processes, verify designs, and collaborate across teams to enhance product manufacturability.

The Senior Memory Circuit Design Engineer will manage the memory design process, perform simulations, and ensure manufacturability while collaborating across teams.

This role involves block-level and sub-system design, timing optimization, circuit optimization, mentoring juniors, and documenting Micro-Architecture Specifications.

The Memory Circuit Design Engineer will design, layout, and optimize memory circuits, manage layout processes, validate designs, and collaborate across teams to enhance product manufacturability and design quality.

The Design Engineer will assist in developing new product designs, manage the layout process, perform verification, and improve design quality.

The role involves designing and optimizing memory/logic/analog circuits, conducting simulations, and managing layout processes while collaborating with multiple teams to ensure product manufacturability.

Design digital IP blocks, drive full-chip integration, collaborate on AI-driven design processes, and mentor teams in advanced memory design.

Develop new memory products by designing DRAM Memory arrays and circuits, optimizing layouts, and leveraging AI tools for design processes.

Responsible for verification of DRAM critical timings, guiding verification efforts, analyzing full chip designs, and developing verification methodologies.

Lead verification architecture and methodology for next-generation DDR memory designs. Develop UVM-based testbenches, verification plans, coverage strategies, and sign-off criteria. Integrate AMS co-simulation and AI/ML-assisted tools for regression, failure classification, and predictive analysis. Mentor verification engineers, collaborate with build teams and EDA vendors, and drive automation and debugging efficiency.

Develop and execute advanced verification environments and UVM-based SystemVerilog testbenches for complex SoC designs (NAND, DDR, PCIe). Define block/subsystem/SoC test plans, run simulations, close functional coverage, debug complex issues, and collaborate with design teams to ensure timely, high-quality verification delivery.

Lead ASIC physical design for enterprise SSD processors/controllers including floorplanning, placement, CTS, routing, RC extraction, STA timing closure, IR/EM analysis, DRC/LVS/ERC, tape-out. Drive APR flow development, PPA analysis, advanced-node (5nm/3nm) implementation, Redhawk-SC/Innovus/Tempus/Calibre tool usage, and manage subsystem team deliverables.

Design and implement semicustom digital blocks (control logic, BIST, DfT); drive RTL-to-GDS flows including synthesis, CTS, P&R and timing closure; perform functional and gate-level verification; develop testbenches and scripting; support silicon bring-up, post-silicon validation, and continuous improvement of semicustom design flows.

The engineer will lead verification efforts, analyze pre-silicon designs, develop test cases for DRAM architectures, and collaborate with international teams while leveraging AI for automation.

The role involves the verification and analysis of memory circuit designs, guiding verification efforts, and developing testing methodologies collaboratively. Candidates should possess skills in circuit analysis, simulation, and scripting.

The Senior Engineer will design and validate on-chip controllers and mixed signal circuitry in NAND FLASH chips, performing RTL design, firmware coding, and full-chip verification.

The role involves owning functional verification for designs, developing tests, debugging failures, driving coverage closure, and leading junior engineers in verification methodologies.

The Staff Engineer Design will engage in block and sub-system design, timing optimization, mentor junior designers, and collaborate on full-chip floorplanning while using various simulation tools.

The Principal Engineer is responsible for designing, analyzing digital circuits for memory products, managing verification, guiding new hires, and ensuring manufacturability through collaboration.