Lead Physical Design Engineer

Posted Yesterday
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3 Locations
In-Office
80K-120K Annually
Senior level
Automotive • Internet of Things • Mobile • Semiconductor • Industrial
The Role
The Lead Physical Design Engineer will manage and execute physical design tasks for high-performance semiconductor ICs, ensuring design integration and resolving issues related to power efficiency, timing, and area.
Summary Generated by Built In

Job Summary:

We are seeking a highly experienced Lead PD Engineer for AI NPU to lead and contribute to the physical design and implementation of complex, high-performance semiconductor integrated circuits. The individual is responsible from RTL synthesis, Floor planning, Placement, CTS, Routing, Timing convergence (STA). The individual contributes to problem solving related to physical design. Contributes to define best Physical design strategy per technology node.

Job Responsibilities
* Execute physical design activities including floorplanning, power planning, place and route, clock tree synthesis, and static timing analysis (STA).
* Collaborate with physical verification (DRC, LVS, Antenna) and resolve related issues.
* Collaborate with power integrity analysis (IR drop, EM) and optimize designs for power efficiency.
* Collaborate with design, verification, and DFT teams to ensure seamless integration and achieve project milestones.
* Analyze and resolve design issues related to timing, area, and power.
* Develop and maintain scripts for automation and efficiency improvements in the physical design flow.
* Contribute to the continuous improvement of physical design methodologies and flows.
* Generate comprehensive reports and documentation of design implementation.

Job Qualifications
* Bachelor's or Master's degree in VLSI or Electronics Engineering or a related field.
* Minimum 8 years of experience in digital physical design of complex SoCs or ASICs.
* Proficiency with industry-standard EDA tools for physical design (e.g., Cadence Innovus/Genus/Tempus or Synopsys Fusion Compiler/PrimeTime, Mentor Calibre).
* Solid understanding and experience of physical design concepts including floorplanning, placement, routing, clock tree synthesis, and physical verification.
* Strong knowledge of Static Timing Analysis (STA) and timing closure techniques.
* Experience with scripting languages such as Tcl, Perl, or Python.
* Familiarity with deep sub-micron process technologies.
* Good understanding of VLSI design principles and semiconductor physics.
* Excellent problem-solving skills and attention to detail.
* Ability to work effectively in a collaborative team environment.
* Good communication skills, both written and verbal.

More information about NXP in India...

#LI-9415

Skills Required

  • Bachelor's or Master's degree in VLSI or Electronics Engineering or a related field
  • Minimum 8 years of experience in digital physical design of complex SoCs or ASICs
  • Proficiency with industry-standard EDA tools for physical design
  • Experience with scripting languages such as Tcl, Perl, or Python
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The Company
HQ: Eindhoven
21,993 Employees
Year Founded: 2006

What We Do

NXP Semiconductors N.V. (NASDAQ: NXPI) enables a smarter, safer and more sustainable world through innovation. As a world leader in secure connectivity solutions for embedded applications, NXP is pushing boundaries in the automotive, industrial & IoT, mobile, and communication infrastructure markets. Built on more than 60 years of combined experience and expertise, the company has approximately 34,500 employees in more than 30 countries and posted revenue of $13.21 billion in 2022. Find out more at www.nxp.com. Privacy Policy: https://www.nxp.com/company/about-nxp/privacy-policy-for-social-media-pages:PRIVACY-POLICY-SOCIAL-MEDIA

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