Top Design Engineer Jobs in Hyderabad

The Staff Engineer will oversee verification activities for DRAM design, utilizing AI tools and simulation to enhance efficiency and provide support for design projects.

Design and optimize full-custom and compiler-based SRAM macros, sense amps, and self-timed circuits. Run SPICE simulations for timing, power, and SNM across corners. Supervise layout teams for FinFET manufacturing, support silicon validation, and debug post-silicon issues while automating workflows with scripting.

Develop and maintain EDA flows and automation for physical ASIC implementation. Optimize PPA for IP cores across advanced foundries, manage regression infrastructure, perform digital implementation with Cadence tools, and create scripts (Python/Tcl/AI) to reduce design turnaround and debug synthesis/LEC issues.

Lead board and IC package design for high-performance SoCs/MCUs from block level to product release. Drive teams, define specifications, perform SI/PI and power design, support SoC bring-up, and liaise with manufacturing for DFM/DFX and packaging delivery.

The role involves owning functional verification for designs, developing tests, debugging failures, driving coverage closure, and leading junior engineers in verification methodologies.

Responsible for developing and integrating foundry rule decks, QA of PDKs, and automating verification processes using various programming languages.

The SR Engineer in Design Verification will simulate, analyze, and debug pre-silicon chip designs, develop test cases, and enhance verification methodologies for DRAM and emerging memory architectures.

The Senior Principal Analog Design Engineer will lead the design and development of analog integrated circuits, mentoring others and overseeing the full lifecycle from concept to silicon validation in automotive and industrial applications.

The Sr. Principal Design Engineer at Cadence will lead SOC verification, develop test plans, and mentor engineers, ensuring high-quality execution of complex projects.

The role involves RTL verification of memory technologies, guiding verification efforts, developing methodologies, and optimizing using AI tools. Requires collaboration on complex chip design projects.

Design, characterize, model, and maintain standard cells for new DRAM technologies. Collaborate with DTCO and international teams, perform timing/power characterization and quality analysis, develop automation/testbench flows and tools, and apply AI-based automation to improve design and characterization productivity.

Lead architecture, design, and delivery of high-speed analog/mixed-signal IP for Die-to-Die/UCIe chiplet systems. Own schematic design, simulation, post-layout sign-off, package co-optimization, silicon bring-up, and cross-team integration to meet performance, power, and reliability targets.

Owns shared silicon library IP from specification through RTL modeling, verification, front-end qualification, and release. Drives lint, CDC, RDC, synthesis, low-power checks, regression pipelines, issue triage, and multi-project integration. Partners with SoC, design verification, physical design, methodology, and EDA teams. Provides technical leadership, design reviews, mentoring, and release-readiness communication across engineering stakeholders.

Lead SoC and subsystem architecture and micro-architecture definition, implement RTL, collaborate with cross-functional teams and vendors, guide floorplanning/synthesis/timing signoff, support pre-silicon verification (simulation, emulation), perform performance/power trade-offs and develop/evaluate design and verification methodologies.

The Principal Engineer will architect and develop Reference Designs using Microchip FPGA products, collaborating with teams to validate designs and enhance product capabilities.

Design high-bandwidth Ethernet/PCIe switches and ARM/MIPS CPU subsystems. Lead digital ASIC work including architecture, micro-architecture, design specification, RTL coding (SystemVerilog/VHDL), FSM design, lint/CDC, constraints, synthesis, and equivalence checking across multiple clock domains.

Design and optimize hardware architecture for AI inference chips, collaborating with software teams to enhance performance and scalability.

The role involves designing high-speed analog circuits, guiding junior designers, and collaborating on AFE interfaces for Ethernet products.

Seeking an Analog Designer with 12-18 years of experience in high-speed design, especially Ethernet and SerDes. Responsibilities include transistor-level design, guiding junior designers, and addressing design challenges.

As a Graduate Design Engineer, you will design telecommunication structures, prepare documentation, manage design risks, and create CAD drafts.

The Staff Digital Design Engineer is responsible for RTL front-end design, IP and full chip integration, and providing technical guidance while ensuring closure of owned blocks through collaboration with teams.

Lead end-to-end verification of complex CPU core microarchitecture using SystemVerilog/UVM. Develop testplans, testbenches, constrained-random tests, scoreboards, checkers, and coverage models. Validate features (OoO, branch prediction, cache coherency, virtual memory), perform ISA-level compliance (RISC-V/ARM/x86), drive regressions, and debug failures across simulation and emulation platforms.

Develop and verify shuttle layout for TI process nodes and tapeouts, ensure DRC and reticle compliance, collaborate with process and PDK teams, and create AI-driven automation tools to accelerate execution.

Leads sustainable drainage design and project delivery for major infrastructure projects. Responsibilities include hydraulic modeling, flood analysis, drainage scheme optimization, risk assessment, BIM and federated model coordination, clash resolution, quality management, client communication, project controls, and team leadership. The role requires independently managing designs from concept through construction, applying British and regional standards, mentoring engineers, and supporting digital automation and continuous improvement initiatives.

Perform full-chip and chiplet-level static timing analysis (STA) from early design stages to signoff. Participate in top-level floorplanning and clock planning, integrate digital partitions and analog IP timing, optimize CAD signoff flows, and define timing/DFT constraints with logic and DFT teams to drive convergence.