Top Design Engineer Jobs in Hyderabad

The Lead Design Engineer will architect and deliver high-speed analog circuits for D2D systems, focusing on UCIe interfaces while collaborating with multiple teams for design optimization and validation.

The role involves owning functional verification for designs, developing tests, debugging failures, driving coverage closure, and leading junior engineers in verification methodologies.

The role involves performing analog timing verification, developing testbenches, executing simulations, analyzing waveforms, debugging failures, and improving verification methodologies.

Design and deliver high-speed analog circuits for Die-to-Die systems. Collaborate on architecture, circuit optimization, and validation.

The engineer will lead verification efforts, analyze pre-silicon designs, develop test cases for DRAM architectures, and collaborate with international teams while leveraging AI for automation.

The role involves the verification and analysis of memory circuit designs, guiding verification efforts, and developing testing methodologies collaboratively. Candidates should possess skills in circuit analysis, simulation, and scripting.

The Principal Engineer will lead digital design efforts, define architectures, mentor team members, and collaborate across teams on advanced PHY design in high-speed technology.

The Lead RTL Design Engineer develops and verifies digital RTL blocks for mixed-signal IPs, collaborating with analog teams and ensuring robust integration into SoCs.

The engineer will verify memory circuits using FastSpice tools, analyze designs, develop testbench scenarios, and collaborate with global teams for verification tasks.

The Principal Engineer is responsible for designing, analyzing digital circuits for memory products, managing verification, guiding new hires, and ensuring manufacturability through collaboration.

The Staff Engineer will lead ASIC verification, creating test plans, developing UVM environments, and ensuring silicon success while mentoring junior engineers.

The Senior Engineer in Analog Design will develop Analog circuits for Memory products, oversee layout processes, conduct verification, and innovate future memory generations.

The SR Engineer in Design Verification will simulate, analyze, and debug pre-silicon chip designs, develop test cases, and enhance verification methodologies for DRAM and emerging memory architectures.

Responsible for the design, layout, and verification of CMOS electrical test structures, improve automation flows, and mentor junior team members.

The role involves full-chip functional verification of non-volatile memory designs, developing verification plans, and collaborating with design teams to ensure functional accuracy.

The Senior Memory Circuit Design Verification Engineer executes verification using FastSpice tools, performs analog SPICE simulations, and collaborates globally to ensure timely design sign-offs and improvements in methodologies.

Responsible for verification of DRAM critical timings, guiding verification efforts, analyzing full chip designs, and developing verification methodologies.

The Principal Engineer will lead NAND Flash Memory design, manage chip verification processes, and collaborate across multiple engineering domains.

As a Principle/Staff Datapath Engineer, you will support design and validation activities for high-speed interfaces in Flash Memory products, engaging in circuit design, optimization, and validation using various simulation tools.

The Mechanical Design Engineer designs and develops mechanical systems for medical devices, collaborates across functions, and ensures compliance with quality standards.

Join NVIDIA as a Physical Methodology Design Engineer, collaborating on GPU design, improving RTL2GDS flows, and implementing efficient chip designs using scripting and EDA tools.

Lead the design and implementation of DFT techniques, including SCAN, ATPG, and JTAG. Collaborate with cross-functional teams on chip tape out and post-silicon bring up, ensuring successful project execution.

The Senior Principal Design Engineer at Cadence will work on DFT and testing for chip designs, requiring extensive experience in ATPG, JTAG, and related methodologies. Responsibilities include chip tape out, test structure design, and cross-domain collaboration to ensure successful project execution.

Lead the development of test plans and verification infrastructure for complex SoCs, ensuring coverage closure through advanced testing methodologies and protocols.

Responsible for micro-architecture and RTL development for High Speed IO IPs, ensuring performance, power, and area requirements are met while collaborating with various teams for verification and validation.