Top Design Engineer Jobs in Hyderabad

Designs and optimizes Flash memory circuits, including row and column drivers, sense amplifiers, and core circuitry. Responsibilities include circuit design, simulation, verification, layout supervision, AMS and RTL integration, array waveform development, floorplanning, documentation, automation, and reliability optimization. The role also mentors junior engineers and collaborates with technology, logic, and project teams across full-chip development.

Designs and develops mechanical and electromechanical test fixtures, environmental test systems, and specialized tooling for optical networking products. Responsibilities include CAD modeling, engineering drawings, BOMs, tolerance studies, documentation, fabrication support, assembly, troubleshooting, validation, and deployment. The role collaborates with engineering teams, technicians, suppliers, manufacturing partners, and vendors to deliver reliable, manufacturable hardware solutions throughout the product development lifecycle.

Lead design verification efforts for memory products by simulating, analyzing, and debugging pre-silicon full-chip designs. Develop test cases, stimulus, test benches, and test vectors; run regressions and improve functional coverage. Contribute to verification methodologies and flows, collaborate internationally, analyze gate-level timing and logic schematics, and identify opportunities for AI-based automation using validated enterprise-approved tools.

Leads verification strategy and execution for automotive connectivity SoCs, developing SystemVerilog/UVM environments, firmware-driven tests, C DPI models, coverage plans, and protocol verification. Debugs RTL, software, and system-level issues; supports functional safety, fault injection, FPGA prototyping, silicon bring-up, and post-silicon validation. Collaborates cross-functionally, improves verification automation and methodology, mentors engineers, and drives verification closure for complex processor-based semiconductor products.

Develop and maintain SystemVerilog/UVM verification environments for automotive connectivity SoCs. Create directed and constrained-random tests, integrate C DPI models, analyze coverage, execute regressions, debug RTL and firmware interactions, and verify processors, communication interfaces, mixed-signal subsystems, and E2B functionality. Support functional safety and ISO 26262 activities, automate workflows, document verification results, and collaborate with design, firmware, architecture, and validation teams.

Develop and maintain SystemVerilog/UVM verification environments for automotive connectivity SoCs. Create directed and constrained-random tests, integrate C DPI models, analyze coverage, execute regressions, debug RTL and firmware interactions, and verify processors, communication interfaces, mixed-signal subsystems, safety mechanisms, and E2B functionality. Collaborate across design, architecture, firmware, validation, and functional safety teams while documenting verification plans, results, and closure activities.

Leads verification strategy and execution for automotive connectivity SoCs. Develops SystemVerilog/UVM environments, firmware-driven tests, C DPI models, coverage plans, and protocol verification. Debugs RTL, embedded software, and system-level issues; supports functional safety, fault injection, FPGA prototyping, silicon bring-up, and post-silicon validation. Collaborates cross-functionally, improves verification automation and methodology, mentors junior engineers, and drives verification closure.

Leads verification strategy and execution for automotive connectivity SoCs. Develops SystemVerilog/UVM environments, firmware-driven tests, C DPI models, protocol verification, coverage plans, and automation. Debugs RTL, software, and system-level issues; supports functional safety, fault injection, FPGA prototyping, silicon bring-up, and post-silicon validation. Collaborates across architecture, design, firmware, safety, and validation teams while mentoring engineers and driving verification closure.

Designs and implements DFT architectures and specifications for ASIC/SoC products. Responsibilities include scan insertion, ATPG pattern development, compression and clock-control insertion, optimizing test coverage and power, and pre- and post-silicon verification and debug. The role also requires gate-level simulation, failure analysis, scripting, and collaboration across product teams.

Develops physical design rules for current and future 3D NAND technologies from conception through production ramp. The role collaborates with process integration, design, CAD, physical verification, and product teams to evaluate layouts, resolve design-rule and mask-generation issues, support DRC, and define algorithms for mask-data generation. It also develops automated and agentic solutions for design-rule coverage and consistency while addressing memory scaling, device physics, and process integration challenges.

Leads ASIC physical design for advanced-node silicon products, including floorplanning, partitioning, placement, clock-tree synthesis, routing, timing and signal-integrity closure, ECOs, power planning, and physical verification. Mentors engineers, leads block closure, interfaces with front-end ASIC teams, and applies low-power techniques such as voltage islands, power gating, and substrate biasing. Requires expertise with Cadence or Synopsys tools, PrimeTime, Perl, Tcl, and 7nm-or-smaller designs.

Leads ASIC logic design and RTL development for complex SoCs. Responsibilities include SoC design and integration, multi-clock and asynchronous interface design, Verilog/SystemVerilog coding, lint and CDC analysis, synthesis and timing evaluation, ECO fixes, formal verification, and implementation of AMBA protocols including AXI, AHB, and APB. Requires strong communication, collaboration, creativity, and motivation to learn.

Design and integrate complex SoCs using RTL, Verilog, and SystemVerilog. Develop multi-clock and asynchronous interfaces, apply ASIC development tools including lint and CDC, and support synthesis, timing analysis, ECO fixes, and formal verification. Implement and work with AMBA protocols including AXI, AHB, and APB, while contributing to clock and reset architecture. Collaborate effectively and communicate clearly across engineering teams.

Lead ASIC design engineer responsible for RTL and logic design, complex SoC design and integration, multi-clock and asynchronous interface development, and ASIC verification activities. The role uses Verilog/SystemVerilog, lint and CDC tools, synthesis, timing analysis, ECO fixes, formal verification, and AMBA protocols including AXI, AHB, and APB. Strong communication, collaboration, creativity, and initiative are required.

Designs and integrates complex SoCs using RTL, Verilog, and SystemVerilog. Responsibilities include multi-clock and asynchronous interface design, ASIC development tooling such as Lint and CDC, timing and synthesis analysis, ECO fixes, formal verification, and AMBA protocol implementation. The role also requires understanding SoC clocking and reset architecture, strong communication, collaboration, creativity, and proactive learning.

Leads ASIC physical design activities for advanced-node silicon products, including floorplanning, placement, routing, clock tree synthesis, timing and signal-integrity closure, physical verification, ECOs, and IR-drop analysis. Provides technical guidance and mentoring, leads physical design engineers, owns block closure, interfaces with front-end ASIC teams, and applies low-power techniques such as voltage islands, power gating, and substrate biasing. Requires expertise with Cadence or Synopsys tools, PrimeTime, Perl, and Tcl.

Design and integrate complex SoCs using RTL coding and Verilog/SystemVerilog. Develop multi-clock and asynchronous interfaces, apply lint and CDC tools, and support synthesis, timing analysis, ECO fixes, and formal verification. Use AMBA AXI, AHB, and APB protocols, along with SoC clocking and reset architectures. Collaborate effectively while contributing proactively to ASIC development and semiconductor engineering projects.

Lead ASIC physical design activities including floor planning, power-grid planning, partitioning, placement, scan-chain reordering, clock-tree synthesis, routing, timing and signal-integrity closure, ECOs, physical verification, DRC, LVS, antenna checks, and IR-drop analysis. The role provides technical mentorship, coordinates with front-end ASIC teams, documents plans, and prioritizes project work.

Serve as the senior technical authority for SoC design verification. Define verification strategies, architectures, methodologies, coverage, automation, readiness, and signoff criteria for complex programs. Lead cross-functional technical initiatives, resolve critical issues, drive innovation, influence engineering leadership, and mentor senior engineers and technical leaders. The role requires deep expertise in SystemVerilog, UVM, verification automation, EDA tools, and UNIX-based design environments.

Design and develop synthesizable RTL for wireless modem digital baseband and PHY-layer IPs. Define microarchitecture, implement DSP blocks, optimize power, performance, and area, and support verification, synthesis, lint, CDC, RDC, integration, and debugging. Collaborate with modem systems, verification, analog, and SoC teams to deliver high-quality wireless IPs for Wi-Fi and low-power IoT devices.

Design, develop, implement, and verify FPGA features supporting RAM, DSP, Ethernet, DDR, and PCIe configurators. Perform design reviews, architecture and documentation feedback, system-level validation, debugging, regression testing, and automation of FPGA development flows. Collaborate with product development teams to deliver robust software and continuously improve design and verification methodologies.

Design and automate CMOS electrical test structures through physical layout, floor planning, placement, wiring, and DRC verification. Develop scalable P-cells and SKILL/SKILL++ automation across technology nodes, enhance EDA and CAD flows using Python and AI-based solutions, and collaborate with global engineering teams. The role also involves process improvement, technical mentoring, and contributing to patents and research publications.

Create and modify 3D mechanical part models using NX or other CAD software. Read mechanical drawings, assemble parts including large assemblies, and extract engineering drawings from 3D models. Teamcenter or other PLM experience is preferred. Candidates must hold a B.Tech, B.E., or Diploma in Mechanical Engineering and have at least two years of 3D CAD experience.

Designs and architects digital components for high-performance data converters and mixed-signal products. Responsibilities include RTL coding, simulation, microarchitecture, lint, CDC, synthesis, formal verification, static timing analysis, physical design collaboration, low-power methodologies, DFT, and EDA tool debugging. The role requires scripting, Unix proficiency, revision-control experience, and collaboration across geographically distributed teams.

Lead physical design implementation and integration at block/subsystem/sub-chip/SoC levels including floorplanning, synthesis, placement, CTS, routing, STA, physical verification, formal equivalency, power integrity (IR-drop/EM) and tapeout readiness. Drive PD flow automation, team delivery against milestones, vendor/IP evaluations, and report progress, issues, and risks to management.