Top Design Engineer Jobs in Hyderabad

The Sr Engineer in Die Design Engineering will oversee TSV & 3D Integration, collaborate across teams, and ensure die design meets advanced packaging requirements.

Responsible for designing and developing software solutions, BSP integration, code optimizations, and debugging hardware/firmware interactions.

The Staff Engineer will work on ASIC physical design, focusing on low power design, timing closure, IR/EM analysis, and tape-out activities, requiring 8+ years of experience in the field.

The Principal Engineer, Design leads the development and design of NAND Flash Memory, innovating features, ensuring manufacturability, and overseeing full chip verification and cross-functional collaboration.

This role involves die design engineering focusing on TSV integration and advanced packaging, collaborating across teams and adopting new technologies while ensuring design reliability and innovation in HBM standards.

Lead full-chip functional verification for non-volatile memory designs using SystemVerilog and UVM. Develop verification plans and testbenches, write assertions and coverage points, run constrained-random tests, debug with digital designers, close coverage to tape-out, and develop/support NAND Flash behavioral models while collaborating with application engineers.

The Design Verification Engineer will own functional verification, develop test plans, create SystemVerilog testbenches, run simulations, and mentor junior engineers while improving verification methodologies.

Design and maintain standard cells for DRAM products, collaborate on architecture, characterize models, develop automation tools, and enhance productivity using AI.

The role involves performing analog timing verification, developing testbenches, executing simulations, analyzing waveforms, debugging failures, and improving verification methodologies.

Design and develop scalable backend services with Python and FastAPI, create modular frontend components in Angular, and collaborate on technical solutions across teams.

Responsible for verification of DRAM critical timings, guiding verification efforts, analyzing full chip designs, and developing verification methodologies.

Design and optimize hardware architecture for AI inference chips, collaborating with software teams to enhance performance and scalability.

The role involves designing high-speed analog circuits, guiding junior designers, and collaborating on AFE interfaces for Ethernet products.

Seeking an Analog Designer with 12-18 years of experience in high-speed design, especially Ethernet and SerDes. Responsibilities include transistor-level design, guiding junior designers, and addressing design challenges.

As a Graduate Design Engineer, you will design telecommunication structures, prepare documentation, manage design risks, and create CAD drafts.

Design and own RTL development for an AI-enabled RISC-V CPU core, including microarchitecture, vector/matrix engines, performance/power/area optimization, and verification support. Collaborate with cross-functional teams for timing, reliability, testability, and SoC integration.

Lead verification architecture and methodology for next-generation DDR memory designs. Develop UVM-based testbenches, verification plans, coverage strategies, and sign-off criteria. Integrate AMS co-simulation and AI/ML-assisted tools for regression, failure classification, and predictive analysis. Mentor verification engineers, collaborate with build teams and EDA vendors, and drive automation and debugging efficiency.

Develop and execute advanced verification environments and UVM-based SystemVerilog testbenches for complex SoC designs (NAND, DDR, PCIe). Define block/subsystem/SoC test plans, run simulations, close functional coverage, debug complex issues, and collaborate with design teams to ensure timely, high-quality verification delivery.

Lead ASIC physical design for enterprise SSD processors/controllers including floorplanning, placement, CTS, routing, RC extraction, STA timing closure, IR/EM analysis, DRC/LVS/ERC, tape-out. Drive APR flow development, PPA analysis, advanced-node (5nm/3nm) implementation, Redhawk-SC/Innovus/Tempus/Calibre tool usage, and manage subsystem team deliverables.

The role involves owning functional verification for designs, developing tests, debugging failures, driving coverage closure, and leading junior engineers in verification methodologies.

The role involves the verification and analysis of memory circuit designs, guiding verification efforts, and developing testing methodologies collaboratively. Candidates should possess skills in circuit analysis, simulation, and scripting.

The Senior Engineer will design and validate on-chip controllers and mixed signal circuitry in NAND FLASH chips, performing RTL design, firmware coding, and full-chip verification.

The Staff Engineer Design will engage in block and sub-system design, timing optimization, mentor junior designers, and collaborate on full-chip floorplanning while using various simulation tools.

The Lead Physical Design Engineer will manage and execute physical design tasks for high-performance semiconductor ICs, ensuring design integration and resolving issues related to power efficiency, timing, and area.

Design Engineer II responsible for DFT and test activities including SCAN/ATPG/JTAG/MBIST, gate-level and SDF timing simulations, memory BIST generation and verification, analog PHY/JTAG testing, scan insertion, STA flows, post-silicon ATE bring-up and debug, Perl/Tcl scripting, and cross-domain issue resolution to support successful tape-out.