Top Design Engineer Jobs in Hyderabad

Design and simulate transistor-level analog/mixed-signal IC blocks (amplifiers, converters, power circuits), define architectures, integrate blocks into mixed-signal systems, present results to teams/customers, support layout, lab evaluation and test, mentor others, and improve design methodologies to meet power, timing and functional objectives.

Design and verify high-speed mixed-signal communication and high-performance digital circuits. Perform RTL coding, simulation, synthesis, timing closure, verification, and debugging at circuit and behavioral levels. Prepare test methods, specifications, datasheets, and demo boards. Collaborate with analog and digital teams and manage multiple tasks to deliver projects on time.

Lead SoC/MCU verification efforts including testplan and testcase creation, coverage closure, requirements traceability, gate-level simulation, and metric-driven verification. Drive verification R&D, collaborate with RTL/DFT/emulation/PD teams, manage risks and milestones, deploy EDA tools, and deliver SoC quality sign-offs and verification methodology improvements.

Lead SoC/MCU verification strategy and execution: create test plans/testcases, drive UVM testbench development, close coverage, perform gate-level simulation and pre-/post-silicon debug, collaborate with architecture/IP/PD/enablement teams, and deliver verification sign-offs and metrics.

Lead design verification for out-of-order CPU cores: own DV strategy and execution, architect SystemVerilog/UVM testbenches, develop constrained-random and scenario libraries, define coverage and assertion sign‑off, debug complex OOO and memory/coherence issues, collaborate with RTL/microarchitecture/post‑silicon teams, and mentor junior DV engineers.

Define design-verification scope and strategy, create test plans from specs, design and implement constrained-random SystemVerilog/UVM testbenches, code and run tests, debug issues, and analyze/collapse results to closure.

Lead verification of complex CPU/SoC IP: plan verification, build constrained-random UVM/SystemVerilog or C/C++ test environments, use SVA/formal tools, debug RTL (Verilog) in simulation/emulation, develop tests and coverage, and close verification gaps to meet tape-out requirements.

Build and maintain design systems and UX engineering for AI-driven CX products. Rapidly prototype, ship features, integrate AI components (LLMs, RAG, knowledge graphs, agents), and work on distributed, event-driven, low-latency systems. Collaborate in a fast-moving, startup-like team to deliver enterprise deployments.

The role involves defining Synthesis & STA flows, managing requirements for SoCs/MCUs, working with EDA vendors, and deploying new tools and methodologies.

The role involves architecting and developing FPGA reference designs, writing RTL code, performing simulations, and collaborating with global teams.

Design and implement high-speed communication protocol IPs for FPGA products using RTL (VHDL/Verilog). Develop testbenches and verification plans, perform timing closure and FPGA implementation, integrate and validate IPs on hardware, debug with lab and vendor tools, and manage project schedules and quality standards.

Lead verification for complex CPU/SoC IP and subsystems: define verification strategies and test plans, build verification environments, run and debug simulations/emulations, apply random-stimulus and coverage-driven techniques, and mentor engineers while improving verification methodologies and tools.

Lead physical verification and power integrity for advanced SoCs: run DRC/LVS/PERC, static/dynamic IR and EM analyses, debug IR-drop/grid weaknesses, collaborate with PD/PnR/foundries, drive EDA automation, and mentor junior engineers to ensure sign-off-ready GDSII tape-outs.

Design, implement, and maintain real-time embedded firmware in C/C++ for resource-constrained wireless systems. Own features from design through release, optimize for memory/power/CPU, debug complex hardware/protocol interactions, contribute to CoEx and multi-protocol solutions, participate in reviews and qualification, and mentor junior engineers.

Lead low-power design verification for complex SoCs using UPF/CPF. Develop test plans, build SystemVerilog/UVM testbenches, create testcases and assertions, perform power-aware verification and debug RTL/UPF issues, drive coverage closure, and collaborate with RTL, architecture, and physical design teams.

Design and deliver synthesizable RTL (Verilog/SystemVerilog) for digital IP from spec to tape-out. Meet PPA targets, support synthesis, timing closure, CDC/RDC, integrate IP into SoCs, collaborate with verification and integration teams, support post-silicon debug, and mentor junior engineers.

Design, develop, and maintain low-level embedded firmware for low-power wireless MCUs. Own hardware feature support through IC lifecycle, optimize for performance and power, debug across hardware/software boundaries, collaborate across teams, contribute to test automation, and mentor engineers.

Lead and execute backend (BE) implementation for complex SoCs from RTL to GDSII, owning timing constraints, STA sign-off, PPA optimization, low-power methodology, EDA flow automation, cross-functional integration, and mentoring a small team to ensure timing closure across modes and corners.

Develop and maintain low-level embedded software and device drivers for low-power wireless MCUs. Own feature development across IC lifecycle, optimize for power and performance, debug hardware/software boundary issues, collaborate with silicon and systems teams, contribute to automated testing and tooling, and mentor other engineers.

Develop and maintain low-level firmware and platform software for SoCs/ASICs across pre-silicon to post-silicon stages. Implement bootloaders, BSPs, device drivers, HALs, and RTOS-based solutions; support silicon and board bring-up, hardware validation, debugging, and performance/power optimization. Collaborate across hardware, verification, and architecture teams, participate in reviews and documentation, and mentor junior engineers.

Develop and maintain low-level embedded software and device drivers for low-power wireless MCUs; support hardware features across IC lifecycle; optimize for performance, power, and memory; debug across software/hardware boundaries; contribute to automated test and tooling; collaborate with cross-functional teams and mentor other engineers.

Define and deploy physical-design methodology for advanced SoCs/MCUs (3/5/16/22nm). Own flows for floorplan, power-plan, P&R, UPF, CTS, and formal/physical verification. Collaborate with cross-functional teams and EDA vendors, resolve blocking issues, benchmark tools, and automate flows using Perl/Tcl/Python to meet low-power, area, and timing convergence goals.

Lead development, testing, and maintenance of a cloud-native supply chain data platform. Design and implement scalable microservices, translate requirements to stories, triage and fix incidents, collaborate in Agile rituals, improve reliability and automation, and mentor peers while ensuring secure, cost-efficient cloud solutions and operational readiness.

The Principal IO Mixed Signal Design Engineer will integrate and verify mixed signal blocks in high-speed IOs for FPGAs, develop custom circuits, and support post-tapeout phases.

Design, implement, and test embedded C/C++ software for Wi‑Fi ICs. Write unit and functional tests, debug with JTAG/GDB and logic analyzers, integrate software with hardware and protocol stacks, participate in code reviews, and improve CI/CD and development best practices.