Top Design Engineer Jobs in Hyderabad

Designs and validates on-chip controllers and mixed-signal circuitry for NAND flash chips. Responsibilities include architecture development, product definition, transistor-level design, test planning, system integration, verification, RTL implementation, firmware development, and full-chip Verilog validation. The role requires expertise in Verilog, digital logic, analog circuits, mixed-mode design, verification CAD tools, and TCL or Perl.

Define and deploy physical-design methodology for advanced SoCs/MCUs (3/5/16/22nm). Own flows for floorplan, power-plan, P&R, UPF, CTS, and formal/physical verification. Collaborate with cross-functional teams and EDA vendors, resolve blocking issues, benchmark tools, and automate flows using Perl/Tcl/Python to meet low-power, area, and timing convergence goals.

The role involves designing and optimizing memory/logic/analog circuits, conducting simulations, and managing layout processes while collaborating with multiple teams to ensure product manufacturability.

Leads SoC and MCU design verification for advanced microcontrollers and microprocessors. Responsibilities include creating verification plans and testbenches, driving coverage closure and requirements traceability, performing simulation and formal verification, managing quality sign-offs, coordinating with architecture, RTL, DFT, emulation, software, and physical design teams, and deploying verification methodologies and EDA tools. The role also owns execution plans, milestone tracking, risk mitigation, executive communications, and continuous improvement across global R&D teams.

Designs and improves PCB load boards used with automated test equipment for semiconductor memory manufacturing. Responsibilities include circuit design and simulation, schematic capture, PCB development, testing, debugging, signal integrity analysis, lab measurements, Python scripting, documentation, engineering change control, prototype qualification, and customer issue resolution. The role works with global engineering, manufacturing, procurement, and contract manufacturing teams while applying AI-assisted tools and continuous improvement practices.

Lead RTL-to-GDSII physical implementation for advanced SoCs, handling floorplanning, power planning, CTS, place-and-route, timing closure, and signoff (STA, SI, EM/IR, DRC/LVS). Optimize PPA and low-power implementation, drive methodology and automation, mentor teams, collaborate across architecture/RTL/DFT/verification/CAD, and adopt AI/Generative/Agentic tools to improve productivity. Custom layout experience for analog/mixed-signal integration is a plus.

Leads block-level digital design and verification for complex automotive networking subsystems. Responsibilities include architecting and implementing RTL IP, optimizing performance, power, and area, performing simulation, synthesis, and timing analysis, supporting verification and debugging, and contributing to architecture reviews and methodology improvements. The engineer collaborates cross-functionally, interacts with customers, handles multi-clock systems and communication protocols, and mentors junior engineers.

Lead block-level digital design and verification for complex automotive networking subsystems. Responsibilities include architecting and maintaining RTL IP, optimizing performance, power, and area, supporting simulation, synthesis, timing closure, and design reviews, and collaborating with verification and cross-functional teams. The role also involves multi-clock system design, on-chip communication protocols, customer interaction, methodology improvements, and mentoring junior engineers.

Design and verify digital integrated circuits and RTL modules through the complete digital design flow, from specification to implementation. Perform synthesis, static timing analysis, and timing closure; develop I2C, SPI, and other interfaces; automate workflows with scripting; collaborate cross-functionally; and document design specifications and test results. The role requires practical Verilog/SystemVerilog experience and typically 2–4 years of relevant experience.

Leads block-level RTL design and verification for complex digital subsystems, including architecture, PPA optimization, timing closure, simulation, synthesis, and multi-clock integration. Collaborates with verification and cross-functional teams, supports design reviews and customer requirements, contributes to methodology improvements, and mentors junior engineers. The role focuses on automotive networking technologies and requires experience with Verilog/SystemVerilog, on-chip protocols, and digital design closure.

Lead DFT strategy, integration, and optimization for NAND flash designs across digital, custom/analog, and array domains. Develop and validate test sequences, firmware, and simulations (Verilog/XA); support first-silicon bring-up, post-silicon validation, failure analysis, and high-volume ramp while collaborating with cross-functional teams.

Leads architecture and transistor-level design of analog and mixed-signal automotive networking ICs. Owns circuits from specifications through tape-out, silicon validation, qualification, and production release. Performs advanced circuit simulation and analysis, directs layout, resolves performance and reliability issues, and collaborates across design, verification, manufacturing, test, and quality teams. Provides technical leadership, conducts design reviews, mentors engineers, supports customer engagements, and drives innovations in automotive Ethernet connectivity.

Designs and owns complex transistor-level analog and mixed-signal IC blocks for automotive Ethernet and wired connectivity. Responsibilities include architecture, schematic design, simulation, layout collaboration, tape-out preparation, silicon bring-up, laboratory characterization, qualification, yield improvement, and production release. The engineer collaborates with global cross-functional teams, evaluates performance and reliability trade-offs, contributes to design reviews, and provides technical guidance to junior engineers.

Lead verification for complex CPU/SoC IP and subsystems: define verification strategies and test plans, build verification environments, run and debug simulations/emulations, apply random-stimulus and coverage-driven techniques, and mentor engineers while improving verification methodologies and tools.

Designs and develops high-performance hardware, leading board design, testing, debugging, and system integration. Collaborates with software and product teams, documents specifications and test plans, ensures quality and regulatory compliance, estimates development work, and mentors junior engineers. The role requires hands-on laboratory experience, EDA tool proficiency, strong hardware design knowledge, and the ability to manage multiple projects independently.

Design and validate on-chip controller and mixed-signal circuitry for NAND flash. Responsibilities include architecture development, transistor-level design, RTL implementation, firmware for NAND operations, full-chip Verilog validation, test planning, system integration, and use of design/verification CAD tools. AI tools encouraged to automate workflows.

Designs and optimizes complex analog power-management IP for advanced DRAM products, including references, regulators, charge pumps, amplifiers, and comparators. Responsibilities include circuit layout, parasitic modeling, simulation, verification, tape-out revisions, manufacturability coordination, and cross-functional collaboration across engineering and manufacturing groups. The role also supports innovation for future memory generations and leverages AI.

Leads verification architecture and methodology for next-generation HBM designs. Responsibilities include developing verification plans, coverage strategies, sign-off criteria, UVM-based testbenches, reusable components, and formal verification approaches. The role partners with build teams, drives verification completeness, manages simulation and regressions, mentors engineers, and influences technical direction. AI-enabled verification and automation using Python or TCL are also encouraged.

Designs and validates FPGA intellectual property using RTL design, logic simulation, compilation, timing closure, and hardware debugging. The role requires programming skills in languages such as C/C++, Perl, Tcl, or Python, plus experience with high-speed I/O protocols including PCIe, Ethernet, CPRI, and JESD204B/C. Responsibilities may also include hardware validation, soft IP packaging, example designs, and testbench development.

Own verification and end-to-end analysis of full-chip gate-level custom memory designs. Develop SystemVerilog and UVM testbenches, test cases, stimulus, test vectors, regressions, and coverage improvements for DRAM and emerging memory architectures. Simulate, debug, and analyze block-level and full-chip designs using digital, mixed-signal, and AMS co-simulation tools. Improve verification methodology through automation and AI-assisted workflows, validate AI outputs, collaborate globally, and mentor team members.

Own verification and end-to-end analysis of advanced DRAM and emerging-memory designs. Develop SystemVerilog/UVM testbenches, test cases, stimuli, regressions, and coverage improvements for block- and full-chip designs. Simulate and debug digital, mixed-signal, and gate-level circuits using industry verification tools. Improve verification workflows through AI-based tools, automation, and scripting while validating AI outputs. Collaborate globally, develop verification methodology, support silicon learning, and mentor newer engineers.

Develop and maintain CI/CD pipelines, build systems, test infrastructure, and release processes for embedded Wi-Fi software. Improve automation, developer productivity, monitoring, telemetry, cloud infrastructure, and operating costs. Establish software delivery standards, metrics, documentation, and workflows while collaborating with infrastructure, SRE, and cross-functional engineering teams.

Develop and integrate synthesizable RTL for mixed-signal IPs, including ADC/DAC interfaces, PLL/DLL controls, power management, and sensor front-ends. Collaborate with analog, verification, architecture, and SoC teams on interface specifications, behavioral modeling, co-simulation, design reviews, lint, CDC, RDC, synthesis readiness, coverage closure, debugging, and full-chip integration. Improve automation, reusable design methodologies, and mixed-signal IP development flows.

Architects, designs, and delivers high-speed analog and mixed-signal IPs for UCIe, PCIe, memory, and SerDes interfaces. Leads design closure across TX/RX, PLL, DLL, CDR, clocking, datapath, and I/O circuits. Directs complex cross-functional IP programs, mentors engineers, drives technical excellence, and may oversee staffing, risks, execution, and customer engagements. The role involves advanced technology nodes, silicon delivery, IP architecture, technology migration, and design reuse.

Own block- and subsystem-level design verification for advanced out-of-order RISC-V CPU cores. Develop SystemVerilog/UVM testbenches, constrained-random and directed tests, reference models, scoreboards, assertions, and coverage strategies. Verify speculative execution, pipelines, memory ordering, caches, TLBs, coherence, exceptions, and flush behavior. Triage regressions, debug complex failures, collaborate with architecture and RTL teams, improve verification methodology, and mentor junior engineers.