Top Design Engineer Jobs in Hyderabad

The Principal Engineer is responsible for designing, analyzing digital circuits for memory products, managing verification, guiding new hires, and ensuring manufacturability through collaboration.

The SR Engineer in Design Verification will simulate, analyze, and debug pre-silicon chip designs, develop test cases, and enhance verification methodologies for DRAM and emerging memory architectures.

The Senior Memory Circuit Design Verification Engineer executes verification using FastSpice tools, performs analog SPICE simulations, and collaborates globally to ensure timely design sign-offs and improvements in methodologies.

The Staff Verification Design Engineer will perform semiconductor verification, focusing on block and chip-level testing, develop strategies, and enhance environments for improved scalability.

The role involves verifying mixed signal circuits, creating simulation environments, and collaborating with various engineering groups to enhance product design and performance.

The Senior Principal Design Engineer at Cadence will work on DFT and testing for chip designs, requiring extensive experience in ATPG, JTAG, and related methodologies. Responsibilities include chip tape out, test structure design, and cross-domain collaboration to ensure successful project execution.

Responsible for micro-architecture and RTL development for High Speed IO IPs, ensuring performance, power, and area requirements are met while collaborating with various teams for verification and validation.

As an ASIC Design Engineer, you will implement BOOT and power management architecture, micro-architecture design, RTL development, and collaborate with cross-functional teams to verify chip correctness.

Design and verify high-speed mixed-signal communication and high-performance digital circuits. Perform RTL coding, simulation, synthesis, timing closure, verification, and debugging at circuit and behavioral levels. Prepare test methods, specifications, datasheets, and demo boards. Collaborate with analog and digital teams and manage multiple tasks to deliver projects on time.

Perform full-chip and chiplet STA convergence from early stages to signoff; participate in top-level floorplanning and clock planning; optimize CAD signoff flows; integrate digital partitions and analog IP timing with PD/RTL teams; define and implement constraints with logic design and DFT for various work modes.

Lead end-to-end highway and roadway drainage design tasks using Civil 3D and drainage design software. Produce detailed drawings, compute quantities, prepare design basis reports, support construction, review designs, and manage project deliverables. Work on UK projects following DMRB and international codes, and support proposals and 3D modelling.

Lead drainage design teams to deliver sustainable drainage (SuDS) schemes and hydraulic/stormwater modelling for UK projects. Produce designs, flood analyses, risk assessments, drawings and BIM/CDE deliverables using industry software, ensure QA/QMS, mentor staff, manage projects from concept to construction and support business development.

Manage and maintain virtual and physical infrastructure for FPGA EDA software, implement and operate CI/CD pipelines, administer VirtualBox and cluster/grid environments (SGE/HTCondor/Kubernetes/AWS), and develop automation scripts in Python and shell to support builds, releases, regression testing, and integration across global teams.

Join the FPGA Software Design team to manage infrastructure, automate builds/releases, and maintain CI/CD and regression frameworks. Implement and operate virtualization, cluster/grid environments, and DevOps tooling, writing automation in Python and shell while collaborating with global engineering teams.

Develop software solutions for Surface devices, collaborating with engineers and optimizing product designs for high-volume consumer products.

Lead design verification for out-of-order CPU cores: own DV strategy and execution, architect SystemVerilog/UVM testbenches, develop constrained-random and scenario libraries, define coverage and assertion sign‑off, debug complex OOO and memory/coherence issues, collaborate with RTL/microarchitecture/post‑silicon teams, and mentor junior DV engineers.

The Staff Verification Design Engineer performs RTL and AMS verification, develops tests, improves verification processes, and collaborates closely with the design team.

The Staff Verification Design Engineer is responsible for block and chip-level verification, creating verification strategies, and supporting post-silicon debug and validation efforts.

Define hardware architectures for AI inference SoCs, oversee design from specification to debug, and collaborate with various teams for performance analysis and validation.

Design ASIC blocks for next generation Microchip FPGA devices, integrating third-party IP and creating new blocks from architecture to production release.

The Principal Engineer will architect and develop Reference Designs using Microchip FPGA products, collaborating with teams to validate designs and enhance product capabilities.

The role involves architecting and developing FPGA reference designs, writing RTL code, performing simulations, and collaborating with global teams.

Design and implement high-speed communication protocol IPs for FPGA products using RTL (VHDL/Verilog). Develop testbenches and verification plans, perform timing closure and FPGA implementation, integrate and validate IPs on hardware, debug with lab and vendor tools, and manage project schedules and quality standards.

Lead end-to-end physical implementation of major IP blocks or full-chip designs: floorplanning, place-and-route, clock tree synthesis, timing closure, physical verification, and automation of flows. Collaborate with RTL, DFT, verification, package, and library teams to meet PPA targets, mentor junior engineers, and drive manufacturability and sign-off across PVT corners.

The role involves defining Synthesis & STA flows, managing requirements for SoCs/MCUs, working with EDA vendors, and deploying new tools and methodologies.