lead Design Engineer

Posted 2 Days Ago
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Hyderabad, Telangana, IND
In-Office
Mid level
Artificial Intelligence • Cloud • Hardware • Software • Semiconductor
The Role
Design and optimize analog mixed-signal circuits for advanced semiconductor technology nodes. Responsibilities include benchmarking PPA, analyzing timing, power, area, and reliability trade-offs, evaluating process design kits, conducting design-technology co-optimization, and using circuit simulation, custom design, reliability, and scripting tools.
Summary Generated by Built In
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Circuit Pathfinding Engineer

The Technology Pathfinding team within the Silicon Solutions Group ensures that our analog mixed-signal (AMS) IP products take maximum advantage of process technology offerings and roadmap from foundries. To do this, we have expertise in technology analysis, design technology co-optimization (DTCO), circuit design and optimization. AI and HPC products demand increasing compute power, higher memory bandwidth and faster chip to chip communication. We work with foundries and our IP design teams to chart the path that gets us there. Join us if you enjoy working with cutting-edge technology nodes (2nm and lower), designing high-speed analog circuits, and hunting down optimizations that improve performance, power and area (PPA).


Role:

  • Circuit design of key AMS circuits to benchmark and optimize PPA in an early stage/experimental technology setting
  • Analyze complex PPA trade-offs related to timing, power, area and reliability
  • Evaluate advanced process development kits (PDKs) from a design and competitiveness viewpoint
  • Conduct DTCO on technology features and foundation IP to maximize PPA 

Requirements:

  • Bachelors degree in Science/Engineering with 2-5 years of industry experience OR  Masters degree in Science/Engineering with 1-4 years of industry experience
  • Industry experience in analog circuit design and layout, preferably on advanced technology nodes
  • Academic coursework on analog design from a reputed university covering CMOS/GAA fundamentals, device-technology interaction such as layout dependent effects and factors affecting circuit PPA
  • Familiarity with industry tools for analog and custom design such as simulation tools (Spectre, Hspice), custom design (Virtuoso, Custom Compiler), and reliability (Voltus, Redhawk)
  • Programming skills in a scripting language like Python, TCL, Perl, etc. Experience in using and building AI agentic flows is a plus.
We’re doing work that matters. Help us solve what others can’t.

Skills Required

  • Bachelor’s degree in Science or Engineering with 2–5 years of industry experience, or Master’s degree in Science or Engineering with 1–4 years of industry experience.
  • Industry experience in analog circuit design and layout.
  • Academic coursework covering analog design, CMOS and GAA fundamentals, layout-dependent effects, device-technology interaction, and circuit PPA factors.
  • Familiarity with analog and custom design tools including Spectre, HSPICE, Virtuoso, Custom Compiler, Voltus, and RedHawk.
  • Programming or scripting experience with Python, Tcl, Perl, or a similar language.
  • Experience with advanced semiconductor technology nodes.
  • Experience using or building AI agentic flows.

Cadence Design Systems Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.

  • Equity Value & Accessibility — A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
  • Healthcare Strength — Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
  • Leave & Time Off Breadth — Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.

Cadence Design Systems Insights

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The Company
HQ: San Jose, CA
8,216 Employees
Year Founded: 1988

What We Do

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.

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