Staff Engineer, Design Enablement

Posted 9 Hours Ago
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Hyderabad, Telangana, IND
In-Office
Senior level
3D Printing
The Role
Define and deploy physical-design methodology for advanced SoCs/MCUs (3/5/16/22nm). Own flows for floorplan, power-plan, P&R, UPF, CTS, and formal/physical verification. Collaborate with cross-functional teams and EDA vendors, resolve blocking issues, benchmark tools, and automate flows using Perl/Tcl/Python to meet low-power, area, and timing convergence goals.
Summary Generated by Built In
Job Description

We are looking for a highly skilled & experienced PD expert to join our Advanced SOCs and MCUs Flows & Methodologies team. The candidate must be experienced, hands-on and have robust understanding of physical design including Floorplan, Power-plan, Place & Route, UPF, CTS. This role requires strong analytical skills, attention to detail, and the ability to work collaboratively with cross-functional teams. Proficiency in relevant EDA tools and a solid understanding of digital design principles are essential for success in these positions

Scope of Responsibilities:

  • As part of the Design Enablement team of the organization, you need to work closely with cross functional teams to develop and define Physical Design methodology to meet advanced SOCs and MCUs and IP level objectives on all geometry nodes (3/5/16/22nm)
  • Your scope of work will cover tools and flows definition, requirement management for Place & Route, UPF, Formal Verification, Floorplan & Power-Plan
  • You will work with EDA Vendors to proactively review latest tools and flows offerings in Physical Implementation domains. Evaluate latest offerings and benchmark with organization used tools, flows, and methodologies.
  • Work with EDA Vendors to review and resolve blocking issues
  • You will be an actor of change for deploying new tools & methodologies across the organization

Specific skills & knowledge :

  • 6-10 years of hands-on experience in Physical Design : UPF, Formal & Physical verification, floorplan, power-plan, Place & Route
  • Proven experience in delivering physical implementation closure methodology ensuring timing & physical convergence
  • Experience in Synopys & Cadence tool sets (Fusion Compiler, Innovus) , low geometry node issues, working with EDA team in reviewing & resolving blocking issues in project
  • Experience in customizing flows & methodology to meet low power & area objectives of SoCs/MCUs
  • Strong scripting skills for Automation and Flow development using PERL/TCL/Python. 
  • Can – do attitude, openness to new environment, people and culture   
  • Strong communication skills (written and verbal), problem solving, attention to detail, commitment to task, and quality focus
  • Ability to work independently and as part of a team

Qualifications

Bachelor or Master or Ph.D. in Electronics Engineering and specialization in VLSI domai

Additional Information

Renesas is an embedded semiconductor solution provider driven by its Purpose ‘To Make Our Lives Easier.’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power.
 
With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘To Make Our Lives Easier.’     
 
At Renesas, you can: 

  • Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things.  
  • Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. 
  • Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day.    

Are you ready to own your success and make your mark?  

Join Renesas. Let’s Shape the Future together.  

Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.

Skills Required

  • 6-10 years hands-on experience in Physical Design (UPF, Formal & Physical verification, floorplan, power-plan, Place & Route, CTS)
  • Proven experience delivering physical implementation closure methodology ensuring timing and physical convergence
  • Experience with Synopsys and Cadence tool sets (Fusion Compiler, Innovus)
  • Experience customizing flows and methodology to meet low power and area objectives for SoCs/MCUs
  • Strong scripting skills for automation and flow development using Perl, Tcl, and Python
  • Experience working with EDA vendors to evaluate tools, benchmark flows, and resolve blocking issues
  • Bachelor's, Master's, or Ph.D. in Electronics Engineering with VLSI specialization
  • Strong communication, problem solving, attention to detail, and ability to work independently and in teams

Renesas Electronics Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Renesas Electronics and has not been reviewed or approved by Renesas Electronics.

  • Fair & Transparent Compensation Feedback suggests pay is generally fair-to-good across many roles, with base pay aligned to prevailing market levels in multiple U.S. locations. Engineering and leadership tracks can be competitive on total compensation, reinforcing a sense that pay can meet market expectations in key job families.
  • Healthcare Strength Feedback suggests core medical, dental, and vision coverage is solid and well-regarded by employees. Day-one eligibility in U.S. roles is described, supporting confidence in access and continuity of care.
  • Leave & Time Off Breadth Feedback suggests PTO, paid holidays, sick time, and parental leave provide a comprehensive time-off framework. Company initiatives like Renesas Day and meeting-light Focus Fridays further support time away and balance.

Renesas Electronics Insights

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The Company
HQ: Toyosu, Tokyo
10,040 Employees

What We Do

We're the world's leading semiconductor manufacturer. Our mission is to make our lives easier and a world that's safer, healthier, greener, and smarter.

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