Top Python Jobs in Hyderabad

The role involves the verification and analysis of memory circuit designs, guiding verification efforts, and developing testing methodologies collaboratively. Candidates should possess skills in circuit analysis, simulation, and scripting.

Design and develop embedded software (bare-metal to embedded Linux) for custom semiconductor test equipment. Write and debug code in C/C++, Bash, and Python, collaborate with electrical, control, and mechanical engineers, support manufacturing and field teams, and maintain lab hardware and documentation. Integrate and improve designs, provide production support, and apply AI-assisted tools to improve efficiency.

Design and maintain standard cells for DRAM products, collaborate on architecture, characterize models, develop automation tools, and enhance productivity using AI.

Responsible for managing enterprise Unix/Linux solutions, supporting OpenShift environments, ensuring compliance, and automating tasks using scripting languages. Collaborates cross-functionally and enhances system performance and reliability.

Lead ASIC validation and SoC prototyping on pre-silicon platforms (HAPS). Develop and execute PCIe/LPDDR/ONFI validation, run C-based SoC simulations with VCS, perform FPGA bring-up/debug using Vivado/Chipscope, write/debug Verilog RTL, and collaborate with design, firmware and overseas teams. Implement prototyping and emulation flows using Protocompiler and Xilinx Ultrascale FPGAs.

Develop and deploy digital twins, multiphysics and structural models, and physics-informed AI to predict and optimize semiconductor process-structure-performance interactions. Apply computational materials science, ML, GenAI/LLMs, and sparse-data methods to accelerate technology development, yield, and reliability. Collaborate with global engineering teams to translate modeling insights into fab-technology co-optimization.

Design and evaluate next-generation memory and storage subsystem architectures. Perform system-level simulations, develop models for controllers/components/interconnects, benchmark application access patterns, and collaborate with design teams to optimize power and performance across software, firmware, and hardware layers.

The role involves leading workload-driven memory architecture and performance strategies, benchmarking, workload characterization, and optimizing systems across mobile and server platforms.

Lead CAD engineer supporting memory layout teams: develop and deploy EDA automation, AI-assisted layout flows, debug physical verification issues, improve productivity, mentor juniors, and evaluate new tools to accelerate reliable CMOS layout delivery.

Build, enhance, optimize, and maintain data-driven applications for Micron’s Data Hub and Integration team. Develop data warehousing and business intelligence solutions using .NET and SQL Server, while applying cloud technologies, microservices, APIs, authentication protocols, containerization, frontend frameworks, and generative AI concepts. Collaborate in a fast-paced environment, meet project timelines, and communicate effectively with technical teams.

Own block-level analog, mixed-signal, and custom digital layout for advanced CMOS designs. Perform DRC, LVS, antenna, yield, and quality verification; support chip integration, ECOs, and layout closure. Develop AI-assisted SKILL, Python, and Tcl automation to improve efficiency and consistency. Collaborate with design, verification, CAD, and senior engineers while mentoring junior layout developers.

Design, develop, and modernize Java backend services and APIs while participating in the full Agile software development lifecycle. Build and maintain GitHub Actions CI/CD pipelines, manage JFrog Artifactory, and automate infrastructure with Terraform. Create secure, optimized Docker images and deploy applications to Kubernetes. Support production releases, troubleshoot incidents, apply DevSecOps practices, and ensure enterprise compliance through testing, monitoring, and code reviews.

Design, implement, and maintain scalable microservices on Azure/AWS; build CI/CD and IaC pipelines; develop RESTful services; optimize cloud infrastructure and costs; mentor engineers; perform design/code reviews; create POCs and define NFR guidelines.

Lead custom analog and mixed-signal layout for LPDDR PHY blocks (datapath, IO, bias, references), drive high-speed interface layout, layout-aware co-design, power/ground/isolation strategies, physical verification and signoff (DRC/LVS/parasitics), post-layout optimization/ECOs, PPA improvements, mentoring, and automation using SKILL/Python/TCL and AI/ML to ensure first-pass silicon success and manufacturability.

Develop and validate NAND testchip test flows, perform pre-silicon digital and analog simulations, define post-silicon testing and characterization, debug testmodes and failures, collaborate with test, design, process and yield teams, and leverage AI to automate tools and workflows to improve build efficiency and device yield.

Lead full-chip floor planning, custom analog and mixed-signal layout, physical implementation, verification signoff, and tape-out for advanced memory and high-speed interface designs. Own DRC, LVS, ERC, EMIR, reliability, and manufacturability closure. Define scalable layout methodologies, drive AI-enabled design automation, lead global cross-functional teams, mentor engineers, and deliver advanced-node semiconductor products.

Lead physical implementation and verification of analog, mixed-signal, and custom digital blocks in advanced CMOS nodes. Own block and full-chip layout, apply AI-assisted and automated flows, perform DRC/LVS/EM/IR and other verification, drive yield-focused optimization, mentor engineers, and collaborate across design, CAD, verification, reliability, and program teams to deliver high-quality layouts on schedule.

Develop, maintain, and support full-stack manufacturing applications. Design, code, optimize databases, implement CI/CD, cloud and DevOps practices, and leverage AI-assisted tools. Collaborate with stakeholders and modernize systems.

Design, build, and support analytics-driven Facilities systems: dashboards, AI-enabled capabilities, front-end interfaces, and data pipelines. Partner with Facilities, IT, and Digital teams to enable automation, predictive insights, standards alignment, and global site support.

Lead verification architecture and methodology for next-generation DDR memory designs. Develop UVM-based testbenches, verification plans, coverage strategies, and sign-off criteria. Integrate AMS co-simulation and AI/ML-assisted tools for regression, failure classification, and predictive analysis. Mentor verification engineers, collaborate with build teams and EDA vendors, and drive automation and debugging efficiency.

Supports reliability, availability, and performance of production applications and platforms. Responsibilities include monitoring, incident response, observability, runbook management, scripting and automation, root-cause follow-up, postmortems, SLO and error-budget adoption, and collaboration with engineering and cloud teams. The role also supports hybrid Azure and Kubernetes environments, operational readiness, AI-assisted investigation, and continuous reduction of alert noise and operational toil.

Drive technology development by conducting advanced electrical device characterization, proposing novel measurement methods, and collaborating with engineering teams to enable device measurements for technology qualification.

The role involves performing failure analysis on NAND components, driving solutions for system development, and innovating testing methodologies while collaborating with multi-functional teams.

The role involves leading NAND Flash memory product validation, developing test algorithms, debugging, and partnering with various engineering teams for product specifications and requirements.

Design and build .NET applications, upgrade existing ones, coordinate with architects, troubleshoot solutions, and ensure application performance.