Top Hardware Engineer Jobs in Portland, OR

Lead system technical ownership for next-generation AI/GPU platforms from architecture handoff to production. Translate requirements into system designs, drive cross-functional execution across hardware/firmware/software/validation/manufacturing/datacenter, resolve system-level tradeoffs (performance, power, thermal, reliability, manufacturability, cost), ensure program readiness and integration, evaluate emerging datacenter technologies, and coordinate with ODMs and suppliers while communicating technical status to leadership.

Lead design and implementation of end-to-end debug and validation solutions for at-scale datacenter hardware. Drive cross-team root-cause analysis, defect reduction projects, test strategy, automation, and large-scale test deployment while communicating progress and technical recommendations to stakeholders.

Lead architecture, design, validation, and troubleshooting of DC-DC power delivery systems for compute, storage, and AI platforms. Drive component qualification, EMI/thermal/reliability testing, supplier and ODM collaboration, root-cause analysis, and mentor junior engineers while influencing product architecture and roadmaps.

Perform deep technical teardown and architectural analysis of AI/datacenter hardware (GPUs, CPUs, ASICs). Drive sample preparation, failure analysis, use FIB/SEM/X-ray tools, interpret design/process trade-offs (DTCO/STCO), co-author research, and expand lab capabilities and tooling.

Design and develop wireless power transfer and energy-harvesting hardware for IoT and wearable devices. Apply power electronics, RF and electromagnetic theory to create ICs and circuits, integrate solutions into scalable systems, optimize energy efficiency, and drive sustainable innovation for large sensor networks.

Develop and maintain transistor-level timing characterization flows, CAD infrastructure, and automation for custom IPs and memory. Collaborate with circuit, memory, STA, and methodology teams; validate Liberty models and SPICE-based characterizations; support platforms, scripts, and EDA vendor tool evaluations.

Develop and maintain full-chip physical implementation flows for SoC designs, including floorplanning, partitioning, hierarchical block integration, placement and routing coordination, power grid planning and IR analysis, CTS strategy integration, and scalable multi-block/multi-power-domain assembly methodologies using Innovus.

Designs and executes hardware test strategies for wireless power products. Develops test specs, fixtures, and software; performs component-level troubleshooting; validates product and fixture qualification; documents results and reports issues to stakeholders.

Lead standardization strategy for optical transport and Ethernet technologies, develop and advocate contributions to standards bodies (ITU‑T, IEEE, OIF, OpenROADM), coordinate with PLMs and R&D, report progress internally, provide technical influence and guidance, and represent Nokia at standards meetings and industry events.

Design, document, and implement PCBA and end-of-line tests and fixtures. Develop and debug flying-probe and automated Windows-based test software, support manufacturing, mentor junior engineers, and improve test coverage and efficiency.

Design, document, and implement PCBA and end-of-line production tests; develop/debug tests on flying-probe platforms; build test automation software and fixtures; configure Windows test platforms; mentor junior engineers; train factory staff; analyze and resolve hardware test issues and improve test coverage and efficiency.

Lead manufacturing engineering for Microsoft cloud hardware: plan factory capacity and layouts, manage suppliers and production risks, standardize processes, implement quality systems (SPC, vision, automation), lead root-cause analysis and continuous improvement (8D, Six Sigma, DFMEA/PFMEA), drive AI/ML and predictive maintenance adoption, validate designs for manufacturability, and deliver metrics and governance for mass production.

The Principal Hardware Engineer will design high-speed digital hardware and maintain product integrity, managing designs from concept to production.

Design, test, and validate next-generation server hardware and components for performance, power, and reliability. Diagnose and resolve hardware issues across engineering and manufacturing, document results, and develop/maintain test scripts. Collaborate with internal teams and OEM/ODM partners to scale platforms for global deployment.

Lead on-site technical authority for datacenter hardware reliability and fleet health. Troubleshoot complex hardware failures, drive root cause analysis and corrective actions, coordinate with vendors and cloud providers, establish maintenance standards and runbooks, support new hardware introductions and spare parts strategy, mentor technicians, and analyze failure trends to improve reliability across large-scale GPU and server deployments.

The Senior Package Layout Engineer will collaborate with teams to design IC substrates, optimize layouts, and improve productivity using Cadence tools.

The role involves optimizing hardware support within a software stack for AI model deployment, collaborating with teams and hardware vendors to enhance performance and portability across platforms.

Design, build, and operate reliable backend systems while mentoring engineers, participating in design discussions, and improving system performance.

As a System Engineer, you'll design, deploy, and maintain cloud systems for AI workloads, troubleshoot complex issues, and collaborate with teams to optimize performance.

As a Senior Hardware Engineer, you'll drive DPU integration into server platforms, execute validation testing, and develop automation for data analysis while collaborating with cross-functional teams and vendors.