Top Senior C++ Jobs in Houston, TX

Design and optimize high-performance C++/CUDA libraries for GPU-based data processing. Improve multi-node GPU communication (UcxExchange), optimize Presto GPU query performance, and lead enhancements across Presto, Velox, and cuDF projects for efficient DataFrame and database acceleration.

Lead architecture and technical direction for Ocient's Loading and Transformation platforms, designing scalable batch and stream ingestion systems. Own ambiguous, cross-team initiatives end-to-end, mentor engineers, and implement high-performance distributed software using modern C++ and/or Java. Partner with product, sales, and customers to translate needs into reliable, petabyte-scale solutions.

Lead engineering of core scheduling and orchestration subsystems for an orbital edge compute platform. Own an MVP for autonomous scheduling across compute node fleets, scale to larger satellite fleets with data sovereignty, design performant and reliable distributed engines, build scheduling and workload-placement logic for intermittent-connectivity edge environments, and provide technical leadership while partnering with cross-functional teams to deliver secure, customer-focused solutions.

Design and implement production-quality system software, tools, and frameworks for enterprise storage systems. Develop and run realistic validation and analysis solutions, debug cross-layer issues (application, OS, driver, hardware), collaborate with firmware/hardware teams, drive technical design, mentor engineers, and evolve internal tooling with AI integrations.

Lead development of the robot platform software: real-time control loops, hardware abstraction, deterministic messaging, and robot API/SDK. Ensure timing guarantees, fault recovery, diagnostics, and long-term API stability. Set platform architecture, mentor engineers, and collaborate with controls, perception, and operations teams to produce reliable on-robot systems for industrial deployments.

Analyze and optimize HPC application performance across CPU and multi-node multi-GPU systems by driving compiler and library improvements. Port and tune applications, evaluate compiler/runtime/driver impacts, and collaborate with compiler development and application engineering teams to deliver performance enhancements.

Lead cross-stack adoption of modern toolchains, build and code-health practices, and performance workflows on NVIDIA CPU platforms. Integrate and validate compilers, linkers, cross-compilation, and CI; profile and optimize large codebases; build automation and playbooks; drive integration blockers to owners and communicate measurable before-and-after results to engineering teams and leadership.

Work as the US-based technical face for Bitmovin's Encoding team: contribute production C++/Java/Kotlin code, triage and resolve customer encoding incidents during US hours, run on-site integrations and workshops, and feed field learnings into sprint planning and the product roadmap.

Build and maintain the GG App across Windows, macOS, and iOS including installers, background services, auto-update systems, enterprise deployment paths, health reporting, AWS backend, and documentation. Lead architecture decisions, mentor engineers, participate in on-call support, and champion AI adoption and automation across engineering.

Design, build, and own operator services that provision, repair, and manage bare-metal GPU servers. Implement secure, extensible code across firmware, imaging, DPU initialization, and network configuration. Operate and monitor GPU fleets at scale, serve on-call rotations to resolve incidents, and apply AI tools across the SDLC while driving automation, telemetry, and reliability improvements.

Lead design and delivery of cloud and AI production systems, partner with stakeholders to translate needs into architecture, ensure security and quality, mentor engineers, and drive customer adoption and scalable reusable solutions across engagements.

Lead architecture and engineering for Azure core platform: define technology requirements, resolve cross-team issues, drive systemic reliability/performance improvements, mentor engineers, support on-call operations, and apply AI/ML to cloud operations.

Design, build, and operate large-scale distributed host networking systems for Azure. Develop host agent services for network configuration, connectivity, and traffic orchestration; improve reliability, observability, and deployment safety; lead incident RCA and mentor engineers while driving architectural direction.

Design and scale high-performance Ethernet and InfiniBand fabrics for hyperscale AI training clusters. Develop ROCE transport and congestion-control mechanisms, topology and routing strategies, telemetry and observability, cluster bring-up, benchmarking, tuning, and cross-vendor co-design to enable low-latency, lossless networks at 10k–100k+ GPU scale.

Work with customers and cross-functional teams to design, build, and deliver cloud-based solutions. Lead design, identify dependencies, mentor engineers, act as DRI and on-call, and improve availability, reliability, observability, and performance. Contribute to open-source assets and collaborate with Microsoft product teams to produce extensible, maintainable code and scalable solution patterns.

Design and implement scalable first-mile networking solutions for Microsoft 365 Substrate and COSMIC. Drive design, dependency identification, coding, optimization, debugging, and on-call monitoring. Analyze production telemetry to improve reliability, performance, and observability. Act as a DRI, lead design and release plans, and collaborate with stakeholders to meet product requirements at global scale.

Participate in full SDLC building and integrating software for DoD customers. Develop C++/Python systems, curate synthetic geospatial raster data, apply TDD, operate in DevSecOps pipelines, and use containerization and CI/CD for deployment and testing.

Define and execute verification plans for block-to-full-chip ASICs using SystemVerilog/UVM. Build testbenches, assertions, constrained-random and directed tests, manage regressions and CI, run simulations, triage failures, close coverage, and support silicon bring-up and post-silicon debug while collaborating across architecture, RTL, DFT, firmware, and physical design teams.

The role involves modeling and verifying analog/mixed-signal IPs, collaborating with teams for optimal performance in communication SoCs.

The role involves designing and optimizing GPU architectures for AI Inference, analyzing hardware-software relationships, and developing performance models.

Develop innovative physical design methodologies for GPUs and SOCs, focusing on PPA improvements and collaboration across multiple teams. Use AI/ML to enhance design efficiency.

The Staff Performance Engineer will optimize latency-critical systems at Helius, focusing on design for low-latency environments, mentoring engineers, and leading performance strategies.

As a Principal Software Engineer, you will architect AI-enabled systems, mentor teams, and guide technical decisions for scalable products.

Design and implement an LLVM-based backend JIT compiler for NVIDIA GPUs. Develop compiler passes and optimizations, focusing on high performance and low compile time. Collaborate with hardware, compiler, and application teams to resolve issues and influence future GPU architectures.

Lead design and implementation of high-throughput, low-latency programmatic bidding systems. Collaborate with ML engineers to deploy real-time inference, optimize distributed microservices, run experiments and quantitative analysis, and partner with product to ship scalable features. Foster operational excellence, mentor engineers, and continuously improve performance and reliability.