Top Design Engineer Jobs

Leads architecture, design, validation, debugging, and production release of complex PCB-based test and measurement hardware. Designs high-speed, analog, mixed-signal, RF, and precision timing circuits; drives signal and power integrity, root-cause analysis, design reviews, and technical tradeoffs. Coordinates cross-functional engineering teams, mentors engineers, leads prototype builds, and develops technical plans to deliver reliable products.

Own clean-sheet mechanical design of small modular gas turbines, including rotors, stators, combustors, cases, bearings, materials, and subsystem interfaces. Perform structural, thermal, and rotordynamic analyses; assess fatigue and durability; design for manufacturability; and work with suppliers and machinists to produce reliable hardware. The role spans conceptual sizing through detailed design and running test articles in a high-ownership seed-stage environment.

The role involves product and system design, CAD development, structural analysis, technical reporting, and project support in engineering.

Develops and maintains engineering drawings, CAD models, specifications, and as-built documentation for radar systems. Reviews layouts for accuracy, standards compliance, and completeness; identifies design deficiencies; supports configuration baselines and production lifecycle management. Requires mechanical design, GD&T, CAD, illustration, product data management, and engineering documentation experience. The role requires an active Top Secret clearance with SCI eligibility and travel up to 25%.

Designs, tests, documents, and reverse-engineers integrated circuits, microelectronic components, ASICs, FPGAs, and related firmware for signal-processing applications. Supports hardware modification for government requirements, develops P&R design flows, integrates tools and libraries, and coordinates engineering work. Senior levels lead designs, mentor engineers, develop reverse-engineering procedures, and oversee component de-processing and firmware retrieval.

Designs sensor timing logic and ISP data paths, contributes to SoC architecture, and performs chip integration and verification. Collaborates on physical design, timing closure, DFT, chip bring-up, silicon debugging, image tuning, and production qualification. Requires at least two years of RTL digital design experience with Verilog or SystemVerilog, scripting proficiency, and experience optimizing power, performance, and area. Image sensor, MIPI, and ISP experience are preferred.

Design and develop transistor-level analog and mixed-signal circuits for CMOS image sensors. Perform block, transistor-level, and whole-chip simulations; create and optimize sensor-array readout layouts using Cadence Virtuoso and Calibre. Collaborate with verification, process, test, and applications teams to debug, characterize, and optimize fabricated image sensors from concept through product release.

Designs and develops transistor-level analog and mixed-signal circuits for CMOS image sensors, including pixel arrays, amplifiers, comparators, data converters, timing controls, and readout circuits. Performs chip floorplanning, layout, simulation, verification, testing, debugging, characterization, and optimization. Collaborates with digital, verification, process, test, and application engineering teams, using Cadence tools, MATLAB, and Excel for analysis and signal processing.

Designs and verifies SoC digital circuits for CMOS image sensors and Wi-Fi 6 architectures. Responsibilities include RTL development, IP integration, clock and reset management, power-aware design, synthesis, DFT, static timing analysis, UVM verification, automation scripting, mixed-signal integration, hardware modeling, chip bring-up, silicon validation, and imaging pipeline optimization. The role collaborates with physical design, analog, firmware, algorithm, and image-quality teams through tape-out and product qualification.

Design and verify digital image sensor and SoC systems, including RTL, IP integration, ISP datapaths, high-speed interfaces, ASIC implementation, and full-chip validation. Perform simulation, synthesis, formal verification, timing analysis, DFT, FPGA prototyping, chip bring-up, silicon debugging, and performance tuning. Develop verification environments using SystemVerilog, SVA, Python, and Perl while collaborating across hardware, software, sensor, analog, and algorithm teams.

Design and integrate digital circuit logic for image sensor and ISP systems, including sensor timing control, data paths, chip architecture, and SoC integration. Collaborate on PPA optimization, physical design, timing closure, DFT, verification, silicon bring-up, debugging, and image quality tuning. Support validation and production readiness while working with analog, digital, algorithm, and application engineering teams.

Designs and integrates digital circuits for image sensors, including sensor timing control and ISP data pipelines. Responsibilities include chip architecture, RTL design, verification, synthesis, timing closure, DFT, full-chip integration, silicon validation, debugging, image tuning, and customer support. The role collaborates with analog, backend, algorithm, and application engineering teams throughout the ASIC development lifecycle.

Designs, integrates, validates, and debugs digital ASIC cores and data pipelines for image sensor SoCs. Responsibilities include RTL and microarchitecture design, timing analysis, synthesis, DFT, formal verification, mixed-signal integration, chip bring-up, silicon validation, and hardware/software co-simulation. Collaborates with physical design, analog, digital, algorithm, and application engineering teams on full-chip integration, tapeout, and performance improvements.

Designs, simulates, verifies, and refines multi-gigabit PAM4 SerDes IP and analog/mixed-signal receiver blocks, including TI-SAR ADCs, CTLE, DFE, and AFE components. Responsibilities include CDR development, high-speed testing with oscilloscopes and BERT, analog-digital interface verification, layout optimization, clock and synchronization design, and IP documentation. The engineer collaborates with system and test teams on high-speed interfaces, packages, boards, and system clocks for image sensor and bridge chip products.

Designs, simulates, verifies, debugs, and characterizes embedded analog and mixed-signal circuits, including high-speed I/O, SerDes, FIFO, CDR, and PLLs. Collaborates with system and test engineers on interfaces, package and board design, and system clocks for image sensor and bridge products. Performs high-speed testing with oscilloscopes and BERT, supports layout optimization, verifies analog-digital interfaces, and documents IP and design specifications.

Lead full-custom analog IC physical design for CMOS image sensors, including column ADC layout, floorplanning, power and clock planning, chip-level routing, parasitic analysis, physical verification, and GDS tape-out. Optimize image sensor performance, area, noise, matching, and power integrity. Develop layout methodologies, automation scripts, design rules, and SVRF files while coordinating top-level implementation resources and schedules.

Designs, simulates, characterizes, and debugs analog mixed-signal integrated circuits, including high-speed I/O, SerDes, PLLs, CDRs, clock trees, serializers, bias circuits, and ESD protection. Performs post-layout signal-integrity analysis, supports circuit layout and floor planning, verifies RTL synchronization blocks, evaluates performance across process, voltage, temperature, noise, and mismatch conditions, and collaborates with system and test engineers on image sensor and bridge-chip products. Documents design reviews, simulation findings, and project lessons learned.

Designs, simulates, verifies, debugs, and characterizes analog and mixed-signal circuits for high-speed interfaces, SerDes, PLLs, CDRs, FIFOs, and clock systems. Collaborates with system and test engineers on image sensor and bridge chip products. Performs high-speed testing with oscilloscopes and BERT, supports layout optimization, verifies analog-digital interfaces, and documents IP and design specifications.

Designs and verifies image sensor processing functions, USB/MIPI high-speed interfaces, and full-chip SoC integration. Responsibilities include chip bring-up, validation, debugging, FPGA development, and architecture, register, interface, and design documentation. Requires digital design expertise covering Verilog RTL, simulation, synthesis, static timing analysis, and formal equivalence. Knowledge of low-power design, FPGA/emulation platforms, SoC architecture, and image processing is beneficial.

Design and verify analog and mixed-signal circuits for CMOS image sensors, including pixel arrays, amplifiers, ADCs, bias generators, and reference circuits. Perform SPICE, corner, Monte Carlo, temperature, process variation, noise, layout, parasitic extraction, and post-layout simulations. Optimize sensor performance, address crosstalk and interference, document designs, and collaborate with digital, architecture, test, verification, and validation teams.

Designs, simulates, verifies, debugs, and characterizes embedded analog and mixed-signal circuits for high-speed interfaces, including SerDes, PLLs, CDRs, and clock systems. Collaborates with system and test engineers on package, board, and system-clock development. Performs high-speed testing with oscilloscopes and BERTs, supports analog/digital interface verification, contributes to layout optimization, and documents IP and design specifications.

Designs, optimizes, and physically implements column-level ADC circuits for CMOS image sensors. Responsibilities include column layout design, cross-product IP comparison, RCX parasitic extraction, supply and power-routing analysis, floorplan optimization, design-rule development, Calibre SVRF debugging, and SKILL scripting. The role collaborates with circuit designers and cross-functional teams to improve ADC performance, silicon efficiency, image quality, and layout robustness.

Design and develop CMOS image sensor analog and mixed-signal circuits in advanced sub-micron technologies. Perform schematic and layout design, simulation, verification, parasitic extraction, and whole-chip integration using industry-standard EDA tools. Collaborate with digital, verification, process, test, and applications teams to define interfaces, debug fabricated sensors, and optimize performance. Develop scripts for simulation and data analysis, conduct laboratory measurements, and contribute innovative circuit research and development.

Designs and verifies image sensor controls, processing functions, and high-speed USB/MIPI interfaces. Performs full-chip integration, verification, chip bring-up, validation, and debugging. Participates in FPGA development and documents architectures, registers, interfaces, and designs. Requires familiarity with Verilog RTL, simulation, synthesis, static timing analysis, and formal verification, plus knowledge of high-performance, low-power design, FPGA platforms, emulation, and SoC architecture.

Design and verify advanced CMOS image sensor analog circuits, including ASRAM and signal-chain building blocks. Perform schematic, layout collaboration, post-layout verification, PVT and Monte Carlo simulation, IR drop and power integrity analysis, and tapeout signoff. Develop Python and Perl automation for simulation and yield analysis. Collaborate across digital, verification, process, and test teams on interface specifications, calibration, silicon bring-up, lab characterization, and performance debugging.