Top Design Engineer Jobs

Reposted 17 Days AgoSaved
In-Office
Corona, CA, USA
151K-177K Annually
Senior level
151K-177K Annually
Senior level
Other
The Electrical Engineer IV will design substation systems, develop engineering calculations, manage projects, and mentor junior engineers while ensuring compliance to industry standards.
Top Skills: EtapMicrosoft Project
Reposted 17 Days AgoSaved
In-Office
5 Locations
164K-312K Annually
Senior level
164K-312K Annually
Senior level
Artificial Intelligence • Cloud • Information Technology • Software
The role involves developing a scalable verification framework for neuromorphic architectures, including test planning, test development, and using AI tools for verification tasks.
Top Skills: Ai ToolsAsic DesignsOvmSilicon EngineeringSoc AcceleratorsUvm
Reposted 17 Days AgoSaved
In-Office
Carmel, IN, USA
129K-139K Annually
Senior level
129K-139K Annually
Senior level
Other • Energy
Analyze operational, economic, and accounting data to evaluate market structures and recommend changes to market design and systems, focusing on efficiency and compliance.
Top Skills: EconometricsOptimization AlgorithmsPower System Analysis SoftwareStatistical Analysis
Senior level
Robotics • Semiconductor • Automation
Design new products and features for the semiconductor industry, produce 3D models, support cross-functional engineering, and ensure reliable product function.
Top Skills: AgileAutocadCreoPlmProe
Reposted 17 Days AgoSaved
In-Office or Remote
2 Locations
155K-185K Annually
Expert/Leader
155K-185K Annually
Expert/Leader
Semiconductor
The IC Design QA Engineer will implement quality gates, monitor IC designs, perform DFMEA, improve processes, and collaborate with teams to ensure product quality.
Top Skills: Asic Design FlowDftHdlPdPdvStaVerilog
Reposted 17 Days AgoSaved
In-Office
Folsom, CA, USA
168K-268K Annually
Senior level
168K-268K Annually
Senior level
Semiconductor • Manufacturing
The Senior Staff Engineer will design and implement SoC features, focusing on RTL design, integration, and validation, particularly in memory and storage technologies.
Top Skills: SystemverilogVerilog
Reposted 17 Days AgoSaved
In-Office
San Jose, CA, USA
163K-253K Annually
Senior level
163K-253K Annually
Senior level
Semiconductor • Manufacturing
Develop verification infrastructure for AI accelerators, lead IP blocks verification, create test plans, mentor engineers, and debug failures in collaboration with cross-functional teams.
Top Skills: C/C++PerlPythonSystem VerilogUvm
Reposted 17 Days AgoSaved
In-Office
River Hills, Austin, TX, USA
52K-83K Hourly
Senior level
52K-83K Hourly
Senior level
Software • Semiconductor • Manufacturing
Responsible for front end design and verification of ASIC design blocks, including architecture definition, logic design, synthesis, and verification through simulation and analysis of timing.
Top Skills: Cadence ConformalCadence Rtl CompilerGitPerlPrimetimeSpyglass LintSvnSynopsys Design CompilerSynopsys FormalityTclVerilog
Reposted 17 Days AgoSaved
In-Office
3 Locations
100K-500K Annually
Senior level
100K-500K Annually
Senior level
Hardware • Manufacturing
The Physical Design Engineer will lead efforts in solving physical design challenges, improve RTL-to-GDS methodologies, and integrate AI/ML solutions into CAD flows, focusing on performance and runtime improvements.
Top Skills: Ai/MlEda ToolsFusion CompilerGdsPythonPyTorchRtlTclTensorFlow
Reposted 17 Days AgoSaved
Hybrid
3 Locations
201K-250K Annually
Senior level
201K-250K Annually
Senior level
Fintech • Software
As a Senior Design Systems Engineer at Carta, you will enhance the Ink component library, optimize AI-driven interfaces, and coach teams on best practices while ensuring high-quality design and code integration.
Top Skills: CSSD3FramerReact
Reposted 17 Days AgoSaved
In-Office
Irvine, CA, USA
120K-170K Annually
Junior
120K-170K Annually
Junior
Aerospace • Other
The Design Verification Engineer will develop ASICs, oversee verification processes, write test plans, and automate testing using Python and MATLAB.
Top Skills: MatlabPythonSystemverilogUvm
Reposted 17 Days AgoSaved
In-Office
Sunnyvale, CA, USA
130K-180K Annually
Mid level
130K-180K Annually
Mid level
Aerospace • Other
As a Design Verification Engineer, you will verify digital ASIC designs, develop test benches, and execute test plans, contributing to the Starlink project.
Top Skills: MatlabPythonSystemverilogUvm
New

Cut your apply time in half.

Use ourAI Assistantto automatically fill your job applications.

Use For Free
Application Tracker Preview
Reposted 17 Days AgoSaved
In-Office
Sunnyvale, CA, USA
210K-280K Annually
Expert/Leader
210K-280K Annually
Expert/Leader
Aerospace • Other
Develop and verify digital ASICs and FPGAs, leading test plans from initiation to completion, and contributing to pre-silicon and post-silicon validation efforts.
Top Skills: AsicsFpgaOvmPythonRtlUvmVmm
Reposted 17 Days AgoSaved
In-Office
Irvine, CA, USA
160K-220K Annually
Senior level
160K-220K Annually
Senior level
Aerospace • Other
Develop and verify digital ASICs for SpaceX's Starlink project; responsibilities include writing test plans, executing tests, and conducting validations.
Top Skills: AsicOvmPythonUvmVmm
Reposted 17 Days AgoSaved
In-Office
Irvine, CA, USA
200K-270K Annually
Expert/Leader
200K-270K Annually
Expert/Leader
Aerospace • Other
The Principal Design Verification Engineer will lead ASIC/FPGA verification, develop test plans, and validate designs for space and ground infrastructure projects, ensuring cutting-edge connectivity solutions for Starlink.
Top Skills: AsicFpgaOvmPythonUvmVmm
Reposted 17 Days AgoSaved
In-Office
Redmond, WA, USA
200K-270K Annually
Expert/Leader
200K-270K Annually
Expert/Leader
Aerospace • Other
Develop and verify digital ASICs and FPGAs for SpaceX's Starlink project, leading verification test plans and collaborating with cross-disciplinary teams.
Top Skills: AsicFpgaOvmPythonRtlUvmVmm
Reposted 17 Days AgoSaved
In-Office
Irvine, CA, USA
120K-170K Annually
Mid level
120K-170K Annually
Mid level
Aerospace • Other
Develop and verify digital ASICs for space deployment, including writing and executing test plans, designing testbenches, and automating test cases using Python and MATLAB.
Top Skills: MatlabPythonSystemverilogUvm
Reposted 17 Days AgoSaved
In-Office
Sunnyvale, CA, USA
170K-230K Annually
Senior level
170K-230K Annually
Senior level
Aerospace • Other
Develop and verify ASIC designs for SpaceX's Starlink system, collaborate with cross-disciplinary teams, and ensure high-performance connectivity solutions.
Top Skills: AsicOvmPythonUvmVmm
Reposted 17 Days AgoSaved
In-Office
Hawthorne, CA, USA
100K-135K Annually
Junior
100K-135K Annually
Junior
Aerospace • Other
The Design Criteria Engineer will develop design criteria for satellite systems, perform peer reviews, guide engineers, and track hardware readiness for launch. Responsibilities include risk mitigation and configuration management, along with process improvements in satellite design and manufacturing.
Top Skills: Erp SystemsExcelMatlabPythonSQLVisual Basic
Reposted 17 Days AgoSaved
In-Office
Redmond, WA, USA
123K-170K Annually
Junior
123K-170K Annually
Junior
Aerospace • Other
The Design Verification Engineer will focus on digital ASIC verification, developing test plans and testbench infrastructures using SystemVerilog, Python, and MATLAB.
Top Skills: DspMatlabPythonRtlSystemverilogUvm
Reposted 17 Days AgoSaved
In-Office
Star, TX, USA
Junior
Junior
Aerospace • Other
Design and build machinery for Starship production, collaborate with engineers, create models in NX, and perform structural analysis.
Top Skills: CatiaNxProeSolidworks
Reposted 17 Days AgoSaved
In-Office
Redmond, WA, USA
160K-220K Annually
Senior level
160K-220K Annually
Senior level
Aerospace • Other
This role involves digital ASIC verification, writing test plans, executing tests, and contributing to pre-silicon and post-silicon validation efforts for spacecraft connectivity technologies.
Top Skills: Asic DesignOvmPythonRtl DesignUvmVmm
Reposted 17 Days AgoSaved
In-Office
Star, TX, USA
Senior level
Senior level
Aerospace • Other
Design, build, and activate machinery for Starship production. Collaborate with teams to enhance design and production processes, perform structural analysis, and create detailed models.
Top Skills: CatiaNxProeSolidworks
Reposted 17 Days AgoSaved
In-Office
San Jose, CA, USA
150K-275K Annually
Senior level
150K-275K Annually
Senior level
Artificial Intelligence • Hardware • Software
The Design Verification Engineer will ensure all architecture requirements are met by collaborating with vendors and internal teams, developing verification environments, and validating external IPs within chip architecture.
Top Skills: AmbaArcArmAxiEthernetPcieSystemverilogUvm
Reposted 17 Days AgoSaved
In-Office
San Jose, CA, USA
150K-275K Annually
Mid level
150K-275K Annually
Mid level
Artificial Intelligence • Hardware • Software
The Design Verification Engineer will verify performance features in ASIC designs, collaborate with teams, and enhance performance models.
Top Skills: AsicPythonSocSystemverilog
All Filters
JobType
New Jobs
Job Category
Experience
Industry
Company Name
Company Size

Sign up now Access later

Create Free Account