Top Design Engineer Jobs

Design and develop heavy off-road mobile equipment from concept through testing and production. Perform steel/aluminum and welded-structure design, hydraulic and electrical control system work, FEA and dynamic analysis, create SolidWorks models and detailed drawings, verify compliance with standards, specify and document testing, manage bills of materials, and collaborate with global design and manufacturing teams to improve manufacturability and product performance.

Lead HVAC, plumbing, and fire protection design for building projects. Create designs, specifications, and calculations using engineering software; support project planning, budgeting, and quality control; collaborate with clients and multidisciplinary teams; perform design reviews, mentor junior staff, and assist through bidding and construction administration while ensuring safety and code compliance.

Perform full-chip and block-level physical design: floorplanning, P&R, clock-tree synthesis, timing closure/STA, low-power implementation, power integrity and IR-drop, and physical verification to take hardmacros from netlist to GDS using industry EDA tools.

Perform physical implementation (place-and-route) and P&R experiments for Adreno GPU cores, including floorplanning, macro placement, CTS, routing, timing closure, STA, low-power (UPF/CPF) flows, physical verification (Calibre DRC/LVS/ERC), and automation scripting to validate new flows and methodologies.

Design and verify microarchitecture and RTL for high-speed PHYs and datapaths. Perform timing closure, timing constraints, PTSI, DFT insertion, and STA. Build HVL-based testbenches, linting and synthesis flows, and work with high-speed IO blocks (PLLs, DLLs, LDOs). Apply low-power techniques and collaborate across distributed teams.

Lead technical scoping, design, and deployment of Instrumental stations for electronics manufacturing. Validate technical requirements with sales, design optics and mechanical nests, work across engineering/operations/quality, and mentor project teams to ensure solutions meet customer business goals and production requirements.

Design and implement RTL and system-level SoC modules, perform logic synthesis and timing analysis, integrate modules into SOC, collaborate with architects and verification teams, support silicon bring-up, and improve design flows and methodologies to enhance efficiency and chip yield.

Lead design and development of switching power MOSFETs (12V–80V): define device architecture, run TCAD simulations, develop process flows, work with fab/process engineers, execute mask/layout tasks, design tests and characterize devices, and support product yield and performance.

Support new product development and manufacturing scale-up for ALD, PVD, and PECVD coatings. Develop and optimize coating processes, design tooling and fixtures using SolidWorks, create drawings/BOMs/work instructions, support prototyping and validation, troubleshoot manufacturing issues, collaborate cross-functionally, work with suppliers, and ensure compliance with SAP/ETQ/EPDM/Accolade and quality systems.

Hands-on role designing, modeling, prototyping, testing, and implementing precision motion systems for semiconductor equipment. Perform FEA, structural dynamics, vibration and thermal analysis, create detailed CAD models and drawings, build and refine prototypes, and collaborate with systems, controls, manufacturing, and physics teams to drive design decisions and product implementation.

Designs, develops, and tests analog and digital circuitry, cable assemblies, data acquisition and electronic control systems for ship and submarine launch control. Performs troubleshooting of electromechanical systems, custom test setup design, EMI mitigation, and supports PCB/CCB and FPGA-related work. Requires US citizenship and ability to obtain Secret clearance. Position based in Sunnyvale, CA with ~10% travel.

Lead physical implementation of custom IP and SoC from RTL through GDSII. Execute synthesis, floorplanning, place-and-route, CTS, STA, power, reliability and physical verification. Analyze signoff results, resolve violations, optimize PPA, and develop/automate physical design methodologies while collaborating with RTL, DFT, timing, verification, and CAD teams.

Implement full-chip and block-level physical design for custom IP and SoC from RTL through GDSII. Execute synthesis, floorplanning, place-and-route, CTS, STA, physical verification and signoff. Optimize power, timing, congestion, and PPA, support DFT integration, root-cause issues, automate flows, and mentor junior engineers across multidisciplinary teams.

Design and microarchitect power-management, reset, and clocking subsystems for high-performance CPU and SoC IP. Specify architectures, implement RTL, perform sandbox verification, collaborate with verification, physical implementation, and software teams to meet frequency, area, and power goals.

Design and microarchitect power management, clocking, and reset solutions for RISC-V CPU and SoC IP. Define requirements, implement RTL, collaborate on verification, physical implementation, and software enablement to meet frequency, area, and power goals.

Design and implement configurable TileLink interconnects, cache controllers, protocol bridges and other uncore infrastructure as RTL generators in Chisel. Integrate with SiFive's Chisel/FIRRTL framework, perform initial sandbox verification, collaborate with verification teams on test plans, document designs, and improve generator tooling for automatic configuration, verification, and packaging.

Design and microarchitect power-management, reset, and clocking solutions for high-performance CPU and SoC IP. Develop RTL, spec microarchitecture, run sandbox verification, collaborate with verification, physical implementation, and software teams to optimize frequency, area, and power and drive designs through tapeout.

Lead design, integration, and validation of custom precision actuator gearing and gearboxes for robotic systems. Define actuator requirements, perform trade studies, build and test prototypes, develop characterization and reliability tests, collaborate with controls, firmware, electrical, and manufacturing teams, and transition designs to production while documenting designs and establishing engineering standards.

Lead design and integration of custom electromechanical robotic actuators from concept through prototype and production. Define requirements, perform trade studies, design electromagnetic components, integrate sensing and encoders, validate prototypes, develop test and reliability methods, analyze failures, and collaborate with controls, firmware, manufacturing, and suppliers to scale designs for production.

Perform RTL-to-GDS physical implementation for CPU blocks: synthesis, floorplanning, place-and-route, clock tree synthesis, STA, power/clock distribution, reliability, and noise analysis. Lead verification and signoff (formal equivalence, DRC/LVS, power integrity). Collaborate with logic, circuit, architecture, EDA vendors, and automation teams to optimize power, frequency, and area and improve physical design methodologies and flows.

Lead end-to-end physical design from RTL to GDS for flagship silicon: synthesis, floorplanning, place-and-route, timing signoff, physical verification, EMIR, formal equivalence, and low-power verification. Coordinate across CAD, RTL/DFT, architecture, and power teams to optimize PPA, drive design flows and tooling, mentor engineers, and ensure delivery of production tape-outs.

Design, validate, and implement tooling, jigs, and fixtures from prototype through production. Lead strain testing and material characterization, create and release detailed drawings, support manufacturing with tolerance analysis and design improvements, manage supplier sourcing and project activities for key accounts.

Perform physical layout and implementation for power grids and 2.5D/3D die-die interconnects; run DRC/LVS and electrical checks; automate flows with scripting; collaborate with SI/PI and manufacturing to develop and evaluate advanced interconnect technologies, RDL/ubump patterns, and testchip roadmaps.

Implement and manage long-distance and local network infrastructure, telemetry and alarming platforms; provision, install, groom, roll, decommission network elements; research and reconcile provisioning database records; validate engineering per project specs; coordinate with NOC/field to verify readiness and resolve data integrity or outage issues.

Design and optimize regional cellular RF networks (CRAN, macros, small cells) balancing capacity, coverage, and cost. Create search areas, cell translations, perform drive testing, prepare FCC/FAA/FAS submissions, support site acquisition, and work with performance teams to reduce lost calls. Require knowledge of CDMA, LTE/VoLTE, link budgets, RF prediction tools, and vendor RAN systems like Ericsson. Proficiency in Siterra/MapInfo and Office applications preferred.