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Reposted 6 Hours AgoSaved
Easy Apply
In-Office
2 Locations
Easy Apply
100K-500K Annually
Entry level
100K-500K Annually
Entry level
Hardware • Manufacturing
As a Staff Design for Test STA Engineer, you will lead the definition and implementation of DFT methodologies and ensure timing closure for AI processors, collaborating with multiple teams to achieve first-pass silicon success.
Top Skills: Cadence TempusDft ArchitectureRisc-VStatic Timing AnalysisSynopsys PrimetimeSystemverilogVerilog
Reposted 23 Days AgoSaved
In-Office
Santa Clara, CA, USA
136K-265K Annually
Senior level
136K-265K Annually
Senior level
Artificial Intelligence • Computer Vision • Hardware • Robotics • Metaverse
As a Senior SOC Design Engineer, you will integrate IP blocks, develop methodologies, streamline SOC design, and ensure high-quality RTL delivery.
Top Skills: Eda ToolsPerlPythonRtl Design
23 Days AgoSaved
Easy Apply
In-Office
San Jose, CA, USA
Easy Apply
207K-230K Annually
Expert/Leader
207K-230K Annually
Expert/Leader
Big Data • Information Technology
Lead RTL-to-GDS physical implementation and signoff for complex connectivity SoCs. Drive PnR, timing closure, extraction, EM-IR, DRC/LVS, and ECO flows; collaborate with RTL, verification, and IP teams to resolve issues and achieve full-chip signoff.
Top Skills: CadenceCxlDdrDftDrcEcoEm-IrEthernetExtractionFormalityLvsNvlinkPciePerlPlace-And-Route (Pnr)Primetime DmsaPythonSerdesStaSynopsysSynthesisSystemverilogTclUalinkVerilog
Reposted YesterdaySaved
In-Office
Bothell, WA, USA
134K-214K Annually
Senior level
134K-214K Annually
Senior level
Healthtech • Telehealth
The Senior Design Quality Engineer leads design control processes, ensuring compliance with quality and regulatory standards, performing risk management, and enhancing product quality through validation and continuous improvement strategies.
Top Skills: Risk Management (Iso 14971)Statistical Tools
Reposted YesterdaySaved
In-Office
Bothell, WA, USA
102K-164K Annually
Mid level
102K-164K Annually
Mid level
Healthtech • Telehealth
The Software Design Quality Assurance Engineer ensures the quality and regulatory compliance of software products by conducting assessments, managing documentation, and leading a compliance team. Key responsibilities include root cause analysis, risk management, and liaising with regulatory bodies.
Top Skills: AgileFda RegulationsIec 62304Iso 14971SafeSdlc
YesterdaySaved
Easy Apply
In-Office
Hawthorne, CA, USA
Easy Apply
160K-225K Annually
Senior level
160K-225K Annually
Senior level
Aerospace • Other
As a Sr. Software Engineer on the Design Software team, develop and maintain software solutions for engineers to manage design data, including 3D graphics and flight simulations, while collaborating closely with engineering staff.
Top Skills: ActivemqAngularApache KafkaC#.NetDockerJavaKubernetesPostgresPythonRabbitMQReactSQL Server
YesterdaySaved
Easy Apply
In-Office
Star, TX, USA
Easy Apply
Junior
Junior
Aerospace • Other
As a Software Engineer in the Design Software team at SpaceX, you will develop reliable software for design data management, enhance operations, and collaborate on software architecture.
Top Skills: ActivemqApache KafkaC#.NetDockerGoJavaKubernetesNeo4JOpenglPostgresPythonRabbitMQScalaSQL ServerThree.JsUnreal EngineVulkan
YesterdaySaved
Easy Apply
In-Office
Hawthorne, CA, USA
Easy Apply
125K-175K Annually
Junior
125K-175K Annually
Junior
Aerospace • Other
As a Software Engineer on the Design Software team at SpaceX, you will develop software solutions for design data management and enhance operational efficiencies. Responsibilities include software development, creating applications, prototyping designs, collaborating on architecture, and integrating design software with manufacturing tools.
Top Skills: ActivemqAngularApache KafkaBazelBuckC#.NetDockerGoGradleJavaKubernetesNeo4JNpmOpenglPantsPipPostgresPythonRabbitMQReactScalaSQL ServerThree.JsVulkan
23 Days AgoSaved
In-Office
Duluth, GA, USA
Expert/Leader
Expert/Leader
3D Printing
Lead architecture and RTL design (Verilog) for high-speed memory buffer ASICs (DDR5/DDR6). Drive synthesis, STA, P&R handoff, DFT, formal verification, ECOs, documentation, reviews, and mentor junior engineers.
Top Skills: Verilog,Rtl,Asic,Ic Design,Dft,Static Timing Analysis,Sta,Synthesis,Place And Route,P&R,Logic Equivalence Checking,Eco,Gate-Level Simulation,Formal Verification,Linting,Cdc,Rdc,Asynchronous Clock Crossing,Atpg,Ate,Ddr5,Ddr6,Mixed-Signal
23 Days AgoSaved
In-Office
Burlington, VT, USA
Mid level
Mid level
Aerospace
Design and deliver mechanical components and systems for small satellite propulsion from concept through production. Collaborate across disciplines, produce production-ready CAD and drawings, support analysis, testing, procurement, BOMs, and customer reviews.
Top Skills: Solidworks,Solidworks Simulation,Ansys,Gd&T,P&Id,Additive Manufacturing,Design For Manufacturing (Dfm),Pressure Vessel Design
Reposted 23 Days AgoSaved
In-Office or Remote
Sunnyvale, CA, USA
150K-220K Annually
Mid level
150K-220K Annually
Mid level
Hardware • Semiconductor • Manufacturing
The Digital Design Engineer develops and verifies silicon IP, creating specs and performance characterizations using C or Python and industry-standard tools.
Top Skills: CFpgaPython
Reposted 23 Days AgoSaved
Easy Apply
In-Office
San Jose, CA, USA
Easy Apply
135K-195K Annually
Senior level
135K-195K Annually
Senior level
Big Data • Information Technology
Oversee planning and execution of physical design for ASICs, collaborating with designers and engineers in developing cutting-edge connectivity solutions for cloud services.
Top Skills: CadenceCosmosCxlEthernetNvlinkPciePerlPythonSynopsysSystem VerilogTclUalinkVerilog
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Reposted 23 Days AgoSaved
In-Office
Irvine, CA, USA
142K-210K Annually
Senior level
142K-210K Annually
Senior level
Artificial Intelligence • Automotive • Semiconductor
Design and verify high-performance analog/mixed-signal circuits for CMOS transceiver/SERDES products, ensuring compliance with performance targets using industry-standard tools.
Top Skills: CmosHsimMatlabSpectreSpiceVerilog
Reposted 23 Days AgoSaved
Easy Apply
In-Office
Hawthorne, CA, USA
Easy Apply
200K-270K Annually
Senior level
200K-270K Annually
Senior level
Aerospace • Other
As a Principal RFIC Design Engineer, you design and develop RF integrated circuits and collaborate on advanced technologies for national security applications. Responsibilities include circuit design, modeling, characterizing, and working with cross-functional teams for product development.
Top Skills: AdsCmosGaasGanHfssMomentumRficSigeSpectre
Reposted 23 Days AgoSaved
Easy Apply
In-Office
Hawthorne, CA, USA
Easy Apply
200K-270K Annually
Senior level
200K-270K Annually
Senior level
Aerospace • Other
The role involves developing advanced RF integrated circuits for MMIC products, managing design, simulation, and testing while collaborating with engineers to implement designs.
Top Skills: AdsAltium DesignerC++CadenceGaasGanHfssMatlabPythonRf Applications
Reposted 23 Days AgoSaved
In-Office
Anoka, MN, USA
76K-122K Annually
Junior
76K-122K Annually
Junior
Consumer Web • Retail
The Design Engineer manages new rifle product development, oversees testing and documentation, collaborates with cross-functional teams, and supports marketing with technical input.
Top Skills: Cad/CamMinitab
Reposted 23 Days AgoSaved
In-Office
Washington, DC, USA
170K-230K Annually
Senior level
170K-230K Annually
Senior level
Information Technology • Consulting
The Sr. Telecommunications Design Engineer III is responsible for delivering technical solutions, O&M support, IT architecture analysis, and ensuring compliance with DoD standards.
Top Skills: AgileIt ArchitectureTelecommunications
Reposted YesterdaySaved
In-Office
2 Locations
136K-265K Annually
Senior level
136K-265K Annually
Senior level
Artificial Intelligence • Computer Vision • Hardware • Robotics • Metaverse
This role involves developing and optimizing standard cell templates, improving library validation, and collaborating with teams in VLSI design at NVIDIA.
Top Skills: C++Cadence SkillPerlPython
Reposted YesterdaySaved
In-Office
3 Locations
136K-265K Annually
Senior level
136K-265K Annually
Senior level
Artificial Intelligence • Computer Vision • Hardware • Robotics • Metaverse
Develop physical design methodologies for graphics processors and SoCs, focusing on chip floorplanning, P&R, timing analysis, and back-end verification.
Top Skills: C++Eda ToolsPerlPython
24 Days AgoSaved
Easy Apply
Remote
United States
Easy Apply
100K-500K Annually
Expert/Leader
100K-500K Annually
Expert/Leader
Hardware • Manufacturing
Design and deliver die-to-die chiplet PHY IP (including PLLs) across the full lifecycle: architecture, circuit design, verification, layout engagement, tape-out, and silicon bring-up. Collaborate cross-functionally to integrate and optimize AMS IP in advanced FinFET nodes, focusing on high-speed I/O, power, performance, and production quality.
Top Skills: Finfet,Pll,Die-To-Die Chiplet Phy,Eda Tools,Serdes,Serializer/Deserializer,Dividers,De-Emphasis,Ctle,Dfe,Bias Generators,Amplifiers,Ldos,Switched-Cap Circuits,Oscillators,Adc,Dac,Tx/Rx Sub-Circuits,Ddr,Pcie,Usb,Silicon Bring-Up,Tape-Out,Layout
Reposted 24 Days AgoSaved
In-Office
2 Locations
75K-114K Annually
Mid level
75K-114K Annually
Mid level
Aerospace
Design, analyze, build, and test fluids and propulsion subsystems for lunar landers, including component requirements and interface negotiations.
Top Skills: AnsysProengineer/CreoPropipingThermal DesktopWindchill
Reposted 24 Days AgoSaved
In-Office
San Jose, CA, USA
127K-184K Annually
Senior level
127K-184K Annually
Senior level
Artificial Intelligence • Internet of Things • Machine Learning
As a Physical Design Engineer, you will execute design tasks from netlist to GDSII, optimize PPA, and collaborate with various teams for FPGA/SoC implementations.
Top Skills: Cadence InnovusCalibrePerlPrimetimePythonStar-RcxSynopsys Ic CompilerTcl
24 Days AgoSaved
In-Office or Remote
New York, NY, USA
156K-275K Annually
Expert/Leader
156K-275K Annually
Expert/Leader
Appliances • Industrial
Technical lead for analog, power-management and mixed-signal ASIC development. Oversee architecture, design, verification, layout, tape-out, lab verification, test-plan development, vendor/test equipment selection, and production support. Drive IC technology strategy and mentor junior staff.
Top Skills: Cadence Virtuoso,Pvs,Assura Drc/Lvs,Qrc Extraction,Voltus Power Analysis,Encounter,Innovus,Cadence Digital Implementation,Circuit Simulation Tools,Excel,Powerpoint
YesterdaySaved
In-Office
Durham, NC, USA
Senior level
Senior level
Artificial Intelligence • Hardware • Automation • Manufacturing
The Staff Analog Design Engineer leads the design and development of complex analog and mixed-signal ICs, mentors junior engineers, and ensures successful project delivery through cross-functional collaboration.
Top Skills: Cadence Design SuiteMatlabSpice
24 Days AgoSaved
In-Office
Fort Valley, GA, USA
Senior level
Senior level
Financial Services • Design
Develop and refine mechanical EV designs using CAD, support prototype development and testing, ensure compliance with FMVSS and customer requirements, produce technical documentation, participate in design reviews, and collaborate with cross-functional teams to ensure manufacturability and feasibility.
Top Skills: Autocad,Matlab,Solidworks,Ev Powertrain Integration,Fmvss
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