Top Senior Hardware Engineer Jobs in Phoenix, AZ

Leads advanced aerospace hardware design from concept through production for next-generation Head-Up Display systems. Responsibilities include schematic capture, PCB design support, hardware validation, troubleshooting, debugging, root-cause analysis, design verification, regulatory compliance, and collaboration with software and systems engineering teams. Provides technical leadership and mentorship while ensuring products meet customer, aerospace, and export-control requirements.

Lead advanced aerospace hardware design from concept through production for Honeywell Anthem displays. Responsibilities include schematic capture, PCB design support, analog and digital circuit development, hardware validation, troubleshooting, debugging, root-cause analysis, design verification, qualification, and stakeholder collaboration. The role also provides technical leadership and mentorship while ensuring compliance with aerospace standards including DO-254 and DO-160.

Leads product engineering, design, development, testing, and validation of advanced hardware for Modular Avionics Unit subassemblies and aerospace applications. Collaborates with cross-functional teams, manages engineering changes and configuration processes, ensures quality and reliability, and drives continuous improvement. The role requires strong hardware design expertise, embedded systems familiarity, and experience with schematic capture, PCB layout, and aerospace product engineering processes.

Designs and validates electrical and electronic components, subsystems, integrated circuitry, and hardware solutions. Develops test plans covering tolerances, form, fit, function, shock, vibration, EMI, safety, reliability, thermal performance, and power. Performs feasibility, margin, validation, modeling, and empirical analyses; collaborates with internal and outsourced engineering partners; evaluates production reliability and supports prototype fabrication for reliable, cost-effective products.

Tests, validates, and troubleshoots next-generation cloud server hardware for performance, power, reliability, and quality. Develops test scripts, documents results, identifies defects, recommends improvements, and resolves hardware issues across engineering and manufacturing environments. Requires hands-on embedded systems debugging, Linux and scripting experience, and knowledge of server architecture, firmware, operating systems, networking, storage, and hardware acceleration technologies.

Owns the hardware lifecycle for GPU and infrastructure assets, including fleet health monitoring, vendor RMA workflows, firmware and BIOS upgrades, burn-in testing, failure investigation, inventory accuracy, capacity planning, spare-parts strategy, runbook creation, and new platform qualification. The role serves as the technical owner of physical compute platforms and supports high-density GPU infrastructure across sites.

Develop and own compute and GPU server platforms from architecture through global deployment. Responsibilities include schematic and layout reviews, design for manufacturability, new product introduction, board and system bring-up, validation, debugging, firmware and BIOS feature management, technology qualification, and vendor coordination. The role requires hands-on server architecture, board-level design, Linux and scripting expertise, platform validation, and five-day-per-week presence in the Cambridge office.

Designs and develops PCB layouts for hardware development tools, including high-speed digital, mixed-signal, and power electronics. Ensures manufacturability, testability, safety, signal integrity, thermal performance, EMC, and RoHS compliance. Maintains PCB, schematic, BOM, drawing, and assembly documentation; creates component libraries and manufacturing outputs; and coordinates with PCB vendors and contract manufacturers.

Validate server hardware components and new platform designs through power, thermal, performance, firmware, and automation testing. Maintain hardware test infrastructure, document technical findings, coordinate with ODM/OEM partners, and collaborate with software teams on BIOS, kernel, and firmware optimization. The role requires expertise in server architectures, validation methodologies, Linux, Python, Bash, Redfish, IPMI, and industry standards including PCIe, NVMe, and DDR.

Lead design and development of ruggedized board-level hardware for defense/aerospace systems. Architect high-speed digital boards (FPGAs, secure processing, PCIe, DDR5, 400G Ethernet), establish design standards, ensure manufacturability and verification, support proposals, and mentor engineering teams through production.

Pipeline hiring for hardware engineers at all experience levels. Work includes circuit board design, schematic capture, component selection and prototype bring-up, hardware debug/testing and failure analysis, integration with firmware/software teams, and design for manufacturability with production handoff.

Lead standardization strategy for optical transport and Ethernet technologies, develop and advocate contributions to standards bodies (ITU‑T, IEEE, OIF, OpenROADM), coordinate with PLMs and R&D, report progress internally, provide technical influence and guidance, and represent Nokia at standards meetings and industry events.

Lead board-level design of ruggedized, high-speed digital hardware from concept through production for defense/aerospace systems. Architect FPGA and CPU-based solutions, ensure signal integrity and manufacturability, establish design standards, support proposals, and collaborate with manufacturing for DFM/DFT.

The Senior/Staff Hardware Design Engineer will lead hardware design and system integration for AI/datacenter motherboard development, ensuring architectural alignment and performing rigorous analysis and optimization.

Provides technical leadership and customer support for Marvell switching, PHY, and processor SoC products. Architects hardware solutions, investigates and reproduces hardware and software issues, performs schematic reviews, debugs boot sequencing and customer-reported problems, and supports Linux BSPs, U-Boot, device drivers, and board designs. Serves as a liaison among customers, Avnet field applications engineers, and Marvell engineering teams, while delivering training and occasional customer-site support.

Lead SI/PI technical work for next-generation ASIC packaging: define design rules, run pre/post-layout SI/PI simulations, analyze substrate SI/PI, collaborate with layout and system teams, mentor engineers, and drive packaging design and validation for high-performance ASICs.

Design and optimize high-speed, high-density ASIC package layouts and substrate breakouts. Perform pinout optimization, routing, placement, stack-up, power distribution, CAD library development, feasibility studies, and productivity methodology improvements while collaborating with package leads and cross-functional teams.

Design and perform physical layout for silicon interposers using Cadence Virtuoso; run DRC/LVS and verification (Calibre, ICV, Thunder); perform feasibility studies, floorplanning, custom layout, and collaborate with package, SI, and technology teams to meet schedule, cost, manufacturability, and electrical goals.

Design, build, and operate reliable backend systems while mentoring engineers, participating in design discussions, and improving system performance.