Top Design Engineer Jobs

Develop and maintain UVM/SystemVerilog SoC-level verification environments and testbenches. Create test plans and strategies to meet coverage goals, develop tests, debug failures, and collaborate with designers to resolve issues across complex SoC architectures.

Staff Engineer in Digital IC Design leading digital integrated circuit architecture and RTL design, verification, timing closure, and implementation. Collaborates across teams, drives design reviews, mentors engineers, and ensures deliverables meet performance, power, and area targets while complying with export control requirements.

Lead digital SoC integration and RTL design efforts, owning portions of chip design through tape-out. Perform RTL development in SystemVerilog, run functional and gate-level simulations, handle CDC, timing closure, clock/reset design, post-silicon debug, and collaborate across architecture, physical design, verification, DFT, and packaging. Deliver micro-architectural specs, develop automation, and use scripting (Python/Tcl) and EDA tools to accelerate development.

Lead SoC-level design verification: create test plans, build and maintain UVM testbenches, develop tests to meet coverage goals, debug failures with designers, and mentor junior engineers.

Lead verification architecture, execution, and delivery for next-generation ASICs. Drive emulation, post-silicon validation, lab bring-up, and PSV. Guide verification methodologies, tools, and front-end ASIC processes. Collaborate cross-functionally, lead teams, and ensure successful tapeout and high-quality ASIC products.

Lead verification of complex SoC and IP designs using UVM and SystemVerilog, define verification strategy and test plans, drive RTL simulation, emulation and post-silicon validation, apply formal verification (SVA), perform deep root-cause debug, manage cross-functional execution, mentor junior engineers, and improve verification infrastructure and automation to achieve sign-off.

Develop and maintain UVM testbenches and verification collateral for complex SoC architectures. Create test plans and strategies, develop tests to meet coverage goals, debug failures, and collaborate with designers to resolve issues. Support verification environments and regression/bug-tracking workflows.

Develop and maintain UVM/SystemVerilog SoC-level verification environments, create test plans and tests to meet coverage goals, debug failures with designers, and mentor junior engineers. Work involves verification tool usage, regression setup, and scripting for automation.

SoC-level design verification engineer responsible for developing and maintaining UVM testbenches, creating verification plans and tests to meet coverage goals, debugging failures with designers, and mentoring junior engineers. Works with verification tools, bug tracking, regression mechanisms, and uses C/C++ and scripting for automation on Linux.

Develop and maintain UVM testbench components and verification environments for complex SoC architectures. Create test plans and strategies, implement tests to meet coverage goals, debug failures, and collaborate with designers to resolve issues.

Lead verification architecture, execution, emulation and post-silicon validation for next-generation ASICs. Drive verification methodologies, lab bring-up, emulation toward successful tapeout, and lead cross-functional ASIC development teams.

Develop and maintain UVM-based verification environments and infrastructure for complex IP/SoC designs. Define verification plans, coverage models, and sign-off criteria. Create and run constrained-random and directed tests, perform coverage analysis, and execute deep RTL debugging and root-cause analysis. Lead verification efforts, mentor junior engineers, improve automation/regression infrastructure, and collaborate with cross-functional teams to drive verification closure and resolve architectural issues.

Lead and own portions of SoC digital design and integration from floorplan to tape-out. Integrate IP blocks, run static checks, simulations and CDC analysis, assist verification, drive timing closure, develop processor IP micro-architecture, and build automation while leveraging EDA and next-generation AI tools.

SoC-level design verification engineer responsible for developing and maintaining UVM testbenches, creating test plans and coverage-driven tests, building verification environments, debugging failures, and working with designers to resolve issues. Requires RTL verification skills and scripting for automation and test infrastructure.

Design and integrate SoC subsystems and internal processor IP from RTL through tape-out. Responsibilities include floorplanning, IP interconnection, static checks, CDC and timing closure, functional and gate-level simulations, post-silicon debug, automation development, and cross-disciplinary collaboration with verification, physical design, DFT, and packaging teams.

Lead architecture and implementation of SystemVerilog/UVM verification environments for complex SoCs. Define test strategies and testplans, write random and coverage-driven tests, debug failures with designers, drive SoC verification methodology, and provide technical leadership and mentoring across distributed verification teams to ensure pre-silicon correctness and productivity improvements.

Lead SoC digital design and integration: own chip subsystems, integrate IP blocks, collaborate on floorplan, drive timing closure, run RTL and gate-level simulations, perform CDC and static checks, deliver micro-architectural specs, leverage EDA and automation tools, lead processor IP design, assist verification and post-silicon debug, and mentor junior engineers.

Design and execute verification plans for complex SoCs using RTL and gate-level simulation. Develop constrained-random UVM testbenches, debug failures with Verdi/VCS, create test vectors, drive coverage models, and collaborate with design teams to validate functionality including AMBA AXI4 and PCIe protocols.

SoC-level design verification engineer responsible for developing and maintaining UVM testbench components and verification environments. Create comprehensive test plans and strategies, develop tests to meet coverage goals, debug failures, and collaborate with designers to resolve issues across complex SoC architectures.

Develop and maintain UVM testbenches and SoC-level verification environments. Create comprehensive test plans and verification strategies, implement tests to meet coverage goals, debug failures, and collaborate with designers to resolve issues.

Design and maintain UVM-based SoC verification environments, create test plans, develop tests to meet coverage, debug failures, collaborate with designers, and mentor junior engineers.

Lead digital SoC design and integration efforts: own a portion of an SoC from floorplan to tape-out, integrate and interconnect IP blocks, run functional and gate-level simulations, perform static checks, CDC and timing closure, support subsystem/chip verification and post-silicon debug, author micro-architectural specs for processor IP, and develop automation (including AI-assisted) to accelerate implementation.

Lead verification architecture, execution, emulation and post-silicon validation for next-generation ASICs. Drive verification methodologies, emulation/PSV efforts to tapeout, bring up ASICs in the lab, mentor and lead cross-functional ASIC development teams, and improve tools and processes to deliver high-quality SoC products.

Lead architecture definition, performance modeling, micro‑architecture and RTL development, and HW/SW co-design for CXL SoC products. Drive cross-functional teams from architecture through tape-out and post‑silicon, interact with customers, and improve productivity for next‑generation datacenter IP/SoC designs.

Develop and maintain scalable UVM-based verification environments and verification plans for complex IP and SoC designs. Create constrained-random and directed testbenches, perform coverage analysis and RTL debugging, drive verification closure, mentor junior engineers, and collaborate with design and architecture teams to resolve system-level issues and improve automation and regression infrastructure.