Top Design Engineer Jobs

Reposted 6 Days AgoSaved
In-Office
Santa Clara, CA, USA
136K-219K Annually
Senior level
136K-219K Annually
Senior level
Artificial Intelligence • Computer Vision • Hardware • Robotics • Metaverse
The engineer will develop verification infrastructure, create functional test plans, and ensure system integration while working with innovative IPs in circuit solutions.
Top Skills: Object Oriented ProgrammingPerlQuestaSvaSystem VerilogTclUvmVcsVerilog
Reposted 6 Days AgoSaved
In-Office
San Jose, CA, USA
Mid level
Mid level
Artificial Intelligence • Software
The Formal Verification Engineer will develop innovative AI-driven solutions for chip design, employing formal methods and collaborating with ML and software teams.
Top Skills: AIC/C++Formal VerificationJaspergoldLlmsMlPythonSvaSystemverilogVcformalVerdiVerilog
Reposted 6 Days AgoSaved
In-Office
San Jose, CA, USA
Mid level
Mid level
Artificial Intelligence • Software
Develop and apply AI techniques to enhance pre-silicon verification methodologies, collaborate with machine learning engineers, and improve design lifecycles.
Top Skills: AICadenceEdaOvmPythonSynopsysSystem VerilogUvmVerilogVhdl
Reposted 6 Days AgoSaved
In-Office
Santa Clara, CA, USA
134K-201K Annually
Senior level
134K-201K Annually
Senior level
Artificial Intelligence • Automotive • Semiconductor
Design, verify, and deliver memory subsystem IP for custom chips. Develop verification plans and environments, analyze simulation failures, and contribute to coverage-driven verification efforts.
Top Skills: DdrHbmLpddrPerlPythonShellSystem VerilogUvm
Reposted 6 Days AgoSaved
In-Office
Santa Clara, CA, USA
134K-201K Annually
Senior level
134K-201K Annually
Senior level
Artificial Intelligence • Automotive • Semiconductor
The role involves developing verification plans for high-speed memory interfaces, building verification environments, and collaborating with design teams for compliance and coverage closure in ASIC/SoC projects.
Top Skills: Coverage ToolsEmulation PlatformsPerlPythonShellSystem VerilogUvm
Reposted 6 Days AgoSaved
Hybrid
Pittsburgh, PA, USA
144K-191K Annually
Senior level
144K-191K Annually
Senior level
Artificial Intelligence • Automotive • Machine Learning • Transportation
The Staff Design Release Engineer will own the design and integration of compute and connectivity subsystems in autonomous vehicles, overseeing technical execution, documentation, and supplier alignment throughout the product lifecycle.
Top Skills: CatiaNxPlmPolarion
Reposted 6 Days AgoSaved
In-Office
2 Locations
Expert/Leader
Expert/Leader
Software
The Principal Design Verification Engineer will lead verification strategies, execute high-performance CPU subsystem verification, and improve methodologies, with a focus on CPU core and coherent interconnect verification.
Top Skills: AutomationCpuEmulationFormal VerificationHardware VerificationObject Oriented ProgrammingRisc-VSoc
Reposted 6 Days AgoSaved
In-Office
2 Locations
70K-120K Annually
Senior level
70K-120K Annually
Senior level
Software
The Staff Design Verification Engineer will lead verification for a cache-coherent interconnect subsystem, focusing on verification planning, execution, and improving methodologies. Key responsibilities include developing robust verification environments and addressing complex verification problems.
Top Skills: PythonSystemverilogUvm
Reposted 6 Days AgoSaved
In-Office
Durham, NC, USA
Senior level
Senior level
Artificial Intelligence • Hardware • Automation • Manufacturing
Lead design verification efforts for power management products, define DV strategies, mentor engineers, and drive methodological innovation across projects.
Top Skills: Ai/Ml ToolsC/C++CadenceEda ToolsJaspergoldMentor/SiemensPerlPythonShellSynopsysSystemcSystemverilogTclUvmVc FormalVerilog
Reposted 6 Days AgoSaved
In-Office
Irvine, CA, USA
210K-300K Annually
Expert/Leader
210K-300K Annually
Expert/Leader
Aerospace • Other
The Principal Design Verification Engineer will lead ASIC and FPGA verification processes, develop and execute test plans, and ensure design integrity through extensive validation processes. They will work with cross-disciplinary teams and contribute to innovative designs for space technology, particularly for Starlink.
Top Skills: AsicFpgaOvmPythonUvmVmm
Reposted 6 Days AgoSaved
In-Office
Austin, TX, USA
Expert/Leader
Expert/Leader
Aerospace • Other
The Principal Design Verification Engineer will verify ASICs/FPGA designs, lead test plans, and ensure designs meet specifications. Collaborating with cross-disciplinary teams, the role involves pre-silicon verification and post-silicon validation.
Top Skills: AsicFpgaOvmPythonUvmVmm
Reposted 6 Days AgoSaved
In-Office
Redmond, WA, USA
210K-300K Annually
Expert/Leader
210K-300K Annually
Expert/Leader
Aerospace • Other
The Principal Design Verification Engineer will lead ASIC and FPGA verification, develop test plans, and validate designs for Starlink's infrastructure. Significant experience in design verification is required.
Top Skills: AsicFpgaOvmPythonUvmVmm
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Reposted 6 Days AgoSaved
In-Office
Star, TX, USA
Senior level
Senior level
Aerospace • Other
The Sr. Mechanical Engineer will design and develop machinery for the Starship production, collaborating with a team to maximize production efficiency.
Top Skills: CadCatiaNxProeSolidworks
Reposted 6 Days AgoSaved
In-Office
Star, TX, USA
Junior
Junior
Aerospace • Other
As a Mechanical Engineer in Machine Design for Starship at SpaceX, you will design custom machinery and infrastructure, collaborate on vehicle design, perform structural analysis, and create engineering models. Responsibilities include supporting machine activation and manufacturing planning while working in a dynamic team environment.
Top Skills: CatiaNxProeSolidworks
Reposted 6 Days AgoSaved
In-Office
Palo Alto, CA, USA
210K-310K Annually
Expert/Leader
210K-310K Annually
Expert/Leader
Aerospace • Other
The principal design verification engineer will lead ASIC verification efforts, ensuring designs meet specifications and are validated through hands-on execution and development of test plans.
Top Skills: AsicFpgaOvmPythonUvmVmm
Reposted 6 Days AgoSaved
In-Office
Chandler, AZ, USA
Expert/Leader
Expert/Leader
Hardware • Semiconductor
The Technical Staff Engineer will design and develop analog ICs for Ethernet and USB products, collaborate with cross-functional teams, and ensure high-quality standards. Responsibilities include creating specifications, performing simulations, and meeting aggressive timelines for product development.
Top Skills: Cadence-VirtuosoDrcEm Analysis ToolsErcLinuxLvsPerlPexSchemeSkillTclUnixVerilog
Reposted 6 Days AgoSaved
In-Office
San Jose, CA, USA
131K-187K Annually
Expert/Leader
131K-187K Annually
Expert/Leader
3D Printing • Marketing Tech • Design
Lead architecture, design, simulation, layout supervision, and silicon validation of high-performance analog/mixed-signal ICs for optical modules. Define specs, run SPICE/Spectre simulations, oversee layout and test plans, perform debug and root-cause analysis, collaborate across disciplines, mentor junior engineers, and produce detailed design documentation.
Top Skills: AdcsAms Simulation EnvironmentsArbitrary Waveform GeneratorCadence VirtuosoCmos Process NodesDacsEda ToolsHigh-Speed AmplifiersNetwork AnalyzerOscilloscopePllsSerdesSpectreSpectrum AnalyzerSpice
Reposted 6 Days AgoSaved
In-Office
San Jose, CA, USA
109K-155K Annually
Senior level
109K-155K Annually
Senior level
3D Printing • Marketing Tech • Design
Design, simulate, and validate high-performance analog and mixed-signal ICs (ADCs, DACs, TIAs, laser drivers) for optical products. Perform SPICE/Spectre simulations, supervise layout and parasitic extraction, develop test plans, participate in silicon characterization and lab debug, collaborate with cross-functional teams, resolve yield and performance issues, document results, and mentor junior engineers.
Top Skills: AdcCadence VirtuosoCmosDacLaser DriverMentor Graphics CalibreNetwork AnalyzerOscilloscopeParameter AnalyzerSpectreSpectrum AnalyzerSpiceSynopsys Custom CompilerTransimpedance Amplifier (Tia)
Reposted 6 Days AgoSaved
In-Office
San Jose, CA, USA
120K-192K Annually
Senior level
120K-192K Annually
Senior level
Software • Semiconductor • Manufacturing
Responsible for verification of networking ASICs, including developing test plans, environments, and executing verification processes using SystemVerilog. Requires strong experience in digital design and verification techniques.
Top Skills: Object Oriented Programming (Oop)PerlPythonSystemverilogUvmVerilog
Reposted 6 Days AgoSaved
In-Office
Sterling, VA, USA
113K-180K Annually
Senior level
113K-180K Annually
Senior level
Artificial Intelligence • Cloud • Social Impact • Software • Wearables
Lead electrical system development for cUAS technology, design schematics and PCB layouts, implement firmware, and ensure compliance with safety standards while collaborating with cross-functional teams.
Top Skills: AltiumArm CortexCC++Esp32KicadOrcadRaspberry PiStm32
7 Days AgoSaved
In-Office
Dearborn, MI, USA
72K-162K Annually
Junior
72K-162K Annually
Junior
Automotive
Deliver and validate Final Assembly tooling to GVOSS standards, coach integrators, own component selection and design sign-off, drive tooling standards, continuous improvement, and manage validation/launch processes. Liaise with program MEs, vendor specialists, and lead VTTO and Tier 2 engagement. Domestic travel ~25%, possible international travel.
Top Skills: GvossExcelMicrosoft OutlookMicrosoft PowerpointMicrosoft WordVirtual Manufacturing Tools
7 Days AgoSaved
In-Office
Auburn Hills, MI, USA
Senior level
Senior level
Automotive
Design, develop, and release engine powertrain sensors (cam, crank, knock, temperature, pressure) from concept to production. Produce 2D drawings and 3D models, specifications, DFMEA and DVP, perform design robustness reviews, resolve production issues, and collaborate with designers, CAE, suppliers, and manufacturing.
Top Skills: 3D FeaCaeDesign For Six Sigma (Green Belt)DfmeaDvpFlow AnalysisExcelMicrosoft PowerpointMicrosoft ProjectMicrosoft WordNx CadRoot Cause Analysis
7 Days AgoSaved
Hybrid
Dearborn, MI, USA
85K-143K Annually
Mid level
85K-143K Annually
Mid level
Automotive
Design and simulate vehicle antennas using HFSS/CST, integrate packaging with styling and body teams, lead Tier 1/2 suppliers through APQP, validate performance via OTA/anechoic and field tests (TIS/TRP), and manage formal production release (ES, SOW, FMEA, quality history) into Ford systems.
Top Skills: Am/FmAnechoic Chamber TestingAntenna DesignApqpC-V2XCellularCstDabEngineering Specifications (Es)FmeaGnssHfssOta UpdatesRf Receiver/TunerSatellite RadioSowTisTrpWers
7 Days AgoSaved
In-Office
Westminster, CO, USA
90K-128K Annually
Senior level
90K-128K Annually
Senior level
Professional Services • Consulting • Automation • Manufacturing
Design electrical control panels, MCCs, and VFD panels for low-voltage industrial systems. Create PLC I/O schematics, panel layouts, BOMs, motor three-line diagrams, cable schedules, and construction scopes. Coordinate with clients, OEMs, contractors, support field start-ups and bid walks, estimate project effort, and travel to client sites (~10%).
Top Skills: Ac Motor DrivesArc FlashAutocadDc Motor DrivesHmisIndustrial Control NetworksMccsMS OfficeNfpa70 (Nec)PlcsUl508AVfds
7 Days AgoSaved
Hybrid
Livonia, MI, USA
65K-166K Annually
Mid level
65K-166K Annually
Mid level
Automotive
Design and release brake control hardware (ABS, ESC, electronic brake boosters) including CAD/BOM management, supplier integration, FMVSS compliance, feasibility and manufacturability analyses, FMEA/functional safety, cross-functional vehicle interface coordination, and support for vehicle, rig, and HIL testing to deliver cost‑effective, production-ready systems.
Top Skills: 3DxBomCadCanFmeaFmvssHardware-In-The-LoopPlmTeamcenter
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