Top Design Engineer Jobs

This role involves verifying SoCs, developing verification environments, writing test plans, and debugging issues, primarily using System Verilog and UVM.

Serve as a technical evangelist for Cadence analog design tools and agentic workflows. Demonstrate product capabilities to customers, resolve customer issues with application engineers, advocate customer needs to R&D, and help define improved use models and user interfaces to advance analog/RF/mixed-signal circuit design workflows.

Lead verification strategy and execution for complex digital and mixed-signal designs. Architect UVM/SystemVerilog environments, develop advanced test benches, define coverage metrics, lead debug and post-silicon validation, mentor junior engineers, and drive methodology improvements while collaborating with design teams and customers.

The Senior Principal Engineer will define and develop system architectures for high-speed industrial products, collaborating closely with customers and stakeholders. Responsibilities include product definition, development, and support, along with participation in business development and technical troubleshooting.

Lead design and development of composite phenolic and elastomer mechanical components from concept through production. Perform CAD modeling, FEA and hand calculations, prototyping, testing, and root-cause analysis. Define scalable manufacturing and assembly processes, create process control documentation, and collaborate with Manufacturing and Quality to improve production and ensure aerospace/defense compliance and production readiness.

Coordinate software release activities across multiple controllers and suppliers, serve as liaison between hardware DREs, function owners and calibration teams, lead HW/SW interface troubleshooting, ensure hardware support for software milestones, identify and escalate risks to leadership.

Provide process engineering and design support for refinery capital and expense projects, troubleshooting, commissioning, and turnarounds. Prepare design packages, perform calculations, evaluate solutions, manage external studies, support safety and hazard analyses, lead multi-functional teams, and mentor junior engineers to ensure safe, compliant, and cost-effective process designs.

Lead digital ASIC verification at block and system level: write and execute test plans, develop test harnesses and regressions, close coverage, support pre-silicon verification, chip bring-up and post-silicon validation, and collaborate with cross-disciplinary teams to verify complex digital designs.

Lead digital ASIC verification at block and system levels: author and execute test plans, develop test harnesses and regressions, drive coverage closure, support pre-silicon verification, chip bring-up and post-silicon validation, and collaborate with cross-disciplinary teams to verify complex designs.

Verify digital ASICs at block and system level: write and execute test plans, build SystemVerilog (UVM and non-UVM) testbenches, run regressions and close coverage, automate tests with Python/MATLAB, and support pre-silicon verification, chip bring-up and post-silicon validation.

Lead digital ASIC verification at block and system levels: write and review test plans, develop test harnesses and sequences, run regressions and close code/functional coverage, and support pre-silicon verification, chip bring-up, and post-silicon validation for complex digital designs.

Develop and execute digital ASIC verification at block and system levels. Build SystemVerilog/UVM and non-UVM testbenches, write test plans, run regressions, close coverage, automate test generation with Python and MATLAB, and support pre-silicon verification, chip bring-up, and post-silicon validation.

Develop and execute digital ASIC verification at block and system levels. Create SystemVerilog/UVM and non-UVM testbenches, write test plans, run regressions, close coverage, automate test generation with Python and MATLAB, and support pre-silicon, chip bring-up and post-silicon validation.

Lead digital ASIC verification at block and system levels: write and execute test plans, develop testbenches and harnesses, run regressions, close coverage, and support pre-silicon verification, chip bring-up, and post-silicon validation for space-qualified ASICs.

Develop and execute digital ASIC verification at block and system level. Build SystemVerilog (UVM and non-UVM) testbenches, write test plans, run regressions, close coverage, automate test generation with Python and MATLAB, and support pre-silicon verification through post-silicon validation and chip bring-up.

Lead Design for Automation (DFA) through new product development, ensuring automation-ready designs. Provide senior manufacturing engineering support for automation, robotics, welding, assembly, tooling, and material handling. Act as SME for automation-critical processes, drive DFA standards and governance, lead PFMEAs and capability reviews, support plant transfers and startups, and apply Lean continuous improvement to reduce cost, risk, and variation.

Design mechanical components and power distribution systems for large-scale BESS and data center infrastructure using SolidWorks. Support prototype testing, design reviews, quoting, supplier collaboration, and continuous improvement while ensuring safety, manufacturability, quality, and sustainability.

Design Verification Engineer responsible for test planning, verification, debugging, adversarial testing, and writing verification environments using HVLs and methodologies (UVM/RVM/OVM). Works with RTL, assertions, code coverage, and simulation acceleration tools; strong communication and scripting skills required.

Design and implement production-grade backend services and platform APIs in Go. Build Kubernetes-native components (controllers, operators, CRDs, webhooks), integrate with CI/CD, observability, and security systems, and apply AI/agentic programming to automate platform workflows and improve developer productivity. Troubleshoot distributed systems and participate in architecture reviews.

Design, simulate, and verify RTL-based ASIC blocks for SoC products. Perform module design, synthesis, RTL/gate-level simulation, pre-/post-layout timing verification, static timing and cross-domain clocking analysis. Support FPGA/emulation bring-up, write detailed design specifications, and collaborate on high-speed data path and state-machine implementations.

Design and document low-voltage electrical hardware and system-level circuitry for medical equipment. Gather requirements, produce high-level and detailed designs, perform power/analog/digital interface design and simulation, create schematics, support PCB/layout and harness development, and transition designs to production while following regulatory and safety standards.

Develop and execute FPGA/ASIC RTL verification tests and test plans using SystemVerilog/UVM. Review designs and RTL, analyze failures, write bug reports, and work with IP vendors and design/firmware engineers to resolve issues.

Develop and extend verification methodology for MAC-layer unit simulations and SoC environments. Architect and implement testbenches, APIs, golden reference models, 802.11 protocol generators/checkers. Define metrics and implement tests for functional correctness, coverage, and performance. Collaborate across teams and use scripting and simulator tools for debug and validation.

Lead and manage electrical engineering design for NYC public school projects, overseeing teams, ensuring code and FDNY compliance, producing design and construction documents, managing submittals, site observations, stakeholder coordination, and implementing technical standards across program projects.

Verify complex hardware systems, including custom IP blocks and SoCs. Develop verification plans, testbenches, and maintain high coverage for reliable silicon.