Top Design Engineer Jobs

Reposted 4 Days AgoSaved
In-Office
San Diego, CA, USA
Mid level
Mid level
Software
Design Verification Engineer responsible for test planning, verification, debugging, adversarial testing, and writing verification environments using HVLs and methodologies (UVM/RVM/OVM). Works with RTL, assertions, code coverage, and simulation acceleration tools; strong communication and scripting skills required.
Top Skills: ArmAssertionsCC++Code CoverageOvmPalladiumPerlRtlRvmShell ScriptingSystemcSystemverilogTclUvmVeloceVera/SpecmanVerilogVhdlVmm
Senior level
Big Data • Fintech • Mobile • Payments • Financial Services • Data Privacy
Design and implement production-grade backend services and platform APIs in Go. Build Kubernetes-native components (controllers, operators, CRDs, webhooks), integrate with CI/CD, observability, and security systems, and apply AI/agentic programming to automate platform workflows and improve developer productivity. Troubleshoot distributed systems and participate in architecture reviews.
Top Skills: Admission WebhooksAksArgo CdClient-GoConsulController-RuntimeCrdDynatraceEksEmbeddingsGithub ActionsGitopsGkeGoGoGrafanaGrpcIamIstioJaegerJenkinsKubebuilderKubernetesLinkerdLlm-Based PlatformsOpenshiftOpentelemetryOperator SdkPkiPrometheusRancherRestSplunkTanzuTektonVaultVector SearchVenafi
Reposted 4 Days AgoSaved
In-Office
Allentown, PA, USA
Mid level
Mid level
Hardware • Semiconductor
Design, simulate, and verify RTL-based ASIC blocks for SoC products. Perform module design, synthesis, RTL/gate-level simulation, pre-/post-layout timing verification, static timing and cross-domain clocking analysis. Support FPGA/emulation bring-up, write detailed design specifications, and collaborate on high-speed data path and state-machine implementations.
Top Skills: AsicCross-Domain Clocking AnalysisEmulation PlatformsFormal VerificationFpgaFpga Board Implementation ToolsLinuxPerlPythonRtlRtl/Gate-Level SimulationStatic Timing AnalysisSynthesis ToolsSystemverilogTclVerilog
Reposted 5 Days AgoSaved
In-Office
Poway, CA, USA
Senior level
Senior level
Information Technology • Professional Services • Software • Consulting
Design and document low-voltage electrical hardware and system-level circuitry for medical equipment. Gather requirements, produce high-level and detailed designs, perform power/analog/digital interface design and simulation, create schematics, support PCB/layout and harness development, and transition designs to production while following regulatory and safety standards.
Top Skills: Altium DesignerArm ProcessorsAutocadCadence Orcad CaptureCanCeCpldDspEmi/EmcEthernetFpgaI2CNecOracle AgilePcb LayoutPic MicrocontrollersPlmPspiceRs232Ul
Reposted 5 Days AgoSaved
In-Office
Menlo Park, CA, USA
Senior level
Senior level
Information Technology • Professional Services • Consulting
Develop and execute FPGA/ASIC RTL verification tests and test plans using SystemVerilog/UVM. Review designs and RTL, analyze failures, write bug reports, and work with IP vendors and design/firmware engineers to resolve issues.
Top Skills: AsicBugzillaDramEthernetFpgaGitMakePciePerlPythonRtlSystemverilogTclUvmVips
Reposted 5 Days AgoSaved
In-Office
San Jose, CA, USA
Senior level
Senior level
Information Technology • Professional Services • Consulting
Develop and extend verification methodology for MAC-layer unit simulations and SoC environments. Architect and implement testbenches, APIs, golden reference models, 802.11 protocol generators/checkers. Define metrics and implement tests for functional correctness, coverage, and performance. Collaborate across teams and use scripting and simulator tools for debug and validation.
Top Skills: 802.11CCadence SimulatorsEthernetLogic SimulatorsMentor ToolsOvmPerlPslPythonSoc VerificationSvaSynopsys SimulatorsSystemverilogTclUvm
Reposted 5 Days AgoSaved
In-Office
Queens, NY, USA
83K-167K Annually
Mid level
83K-167K Annually
Mid level
Industrial
Lead and manage electrical engineering design for NYC public school projects, overseeing teams, ensuring code and FDNY compliance, producing design and construction documents, managing submittals, site observations, stakeholder coordination, and implementing technical standards across program projects.
Top Skills: CommissioningData/TelecommunicationsElectrical Load CalculationsFdny Fire Alarm RequirementsFire Alarm System DesignIp-Based Security Camera SystemsLighting Control SystemsNew York City Building CodeNew York City Electrical CodeNfpa-70 (National Electrical Code)Nyc Energy Conservation Code (2020/2025)Public Address SystemsService Room Layout
Reposted 5 Days AgoSaved
Hybrid
San Francisco, CA, USA
226K-445K Annually
Mid level
226K-445K Annually
Mid level
Artificial Intelligence • Machine Learning • Generative AI
Verify complex hardware systems, including custom IP blocks and SoCs. Develop verification plans, testbenches, and maintain high coverage for reliable silicon.
Top Skills: QuestaSystemverilogUvmVcsVerdi
Reposted 5 Days AgoSaved
Hybrid
Austin, TX, USA
90K-110K Annually
Mid level
90K-110K Annually
Mid level
Energy • Utilities • Renewable Energy
As a Project Engineer, you will lead design efforts for gas distribution and transmission systems, mentoring junior engineers while ensuring compliance and technical accuracy on mid-sized projects.
Top Skills: Gas DistributionGas Transmission SystemsNatural Gas Design
Reposted 5 Days AgoSaved
In-Office
Hawthorne, CA, USA
100K-135K Annually
Junior
100K-135K Annually
Junior
Aerospace • Other
The Design Criteria Engineer will develop design criteria for satellite systems, perform peer reviews, guide engineers, and track hardware readiness for launch. Responsibilities include risk mitigation and configuration management, along with process improvements in satellite design and manufacturing.
Top Skills: Erp SystemsExcelMatlabPythonSQLVisual Basic
Reposted 5 Days AgoSaved
In-Office
11 Locations
136K-170K Annually
Senior level
136K-170K Annually
Senior level
Appliances
The Project Engineer III will mentor others, serve as a technical expert in power systems consulting, manage projects, and ensure safety practices. Responsible for scope, budget and schedule review, and providing innovative solutions in substation physical design.
Top Skills: Electric Power SystemsPower Systems ConsultingSel Equipment
Reposted 5 Days AgoSaved
In-Office
2 Locations
Senior level
Senior level
Software
The Staff Design Verification Engineer drives the verification of cache-coherent interconnect subsystems, focusing on CXL protocols and integration, defining verification plans, and improving overall verification quality through collaboration and mentorship.
Top Skills: PythonSystemverilogUvm
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Reposted 5 Days AgoSaved
In-Office
4 Locations
Internship
Internship
Software
The intern will join the Design Verification Infrastructure team to develop and maintain the Verification Platform, enhancing design verification technologies through collaboration and software development in Scala and Python.
Top Skills: ChiselCirctEda ToolsPythonScala
Reposted 5 Days AgoSaved
In-Office
South San Francisco, CA, USA
125K-291K Annually
Senior level
125K-291K Annually
Senior level
Biotech
The engineer designs analog and mixed-signal chips, manages layout processes, oversees verification plans, and runs complex simulations. Also responsible for guiding junior staff and consulting with users and vendors for alignment on project goals.
Top Skills: CmosFinfetSystemverilogVerilog Ams
Reposted 5 Days AgoSaved
In-Office
San Jose, CA, USA
147K-278K Annually
Senior level
147K-278K Annually
Senior level
Cloud • Information Technology • Internet of Things • Professional Services • Software
Lead verification strategy and execution for complex ASIC/SoC programs. Architect scalable UVM/SystemVerilog-based verification infrastructure, drive emulation/prototyping and formal verification, mentor teams, influence ASIC design for testability, and lead root-cause analysis during silicon bring-up and post-silicon validation.
Top Skills: CC++EmulationFormal VerificationPerlPrototypingPythonSystemverilogUvm
Reposted 5 Days AgoSaved
In-Office
San Jose, CA, USA
136K-252K Annually
Mid level
136K-252K Annually
Mid level
Cloud • Information Technology • Internet of Things • Professional Services • Software
Design and maintain block/cluster/top-level ASIC verification environments, build reusable testbenches, create and run constrained-random and directed tests, implement coverage, run gate-level simulations, support emulation and post-silicon bring-up, and collaborate with designers and software teams to debug complex chip issues.
Top Skills: CxlDdrEmulationEthernetGate Level SimulationHapsIevP4PalladiumPciePerlPythonRdmaRtlSystemverilogTcpUvmVc FormalVeloceZebu
Reposted 5 Days AgoSaved
In-Office
San Jose, CA, USA
147K-278K Annually
Senior level
147K-278K Annually
Senior level
Cloud • Information Technology • Internet of Things • Professional Services • Software
Lead and define ASIC verification strategy and methodology across programs. Architect scalable verification infrastructure, mentor teams, drive cross-functional improvements, influence ASIC design for verifiability, and lead root-cause analysis during bring-up and post-silicon validation.
Top Skills: C/C++EmulationPerlPythonSystem VerilogUvm
Senior level
Robotics • Semiconductor • Automation
Design new products and features for the semiconductor industry, produce 3D models, support cross-functional engineering, and ensure reliable product function.
Top Skills: AgileAutocadCreoPlmProe
Reposted 5 Days AgoSaved
Hybrid
Conshohocken, PA, USA
95K-130K Annually
Mid level
95K-130K Annually
Mid level
Consulting
Provide technical leadership and design oversight for highway engineering projects. Develop design criteria, alignments, pavement, signing, MOT, utility coordination, specifications, quantities, estimates, and 3D models in OpenRoads. Perform technical reviews, coordinate with discipline leads and PMs, contribute to staffing and proposals, prepare technical presentations, and mentor staff to meet client scope, schedule, budget, and quality standards.
Top Skills: AutocadMicrostationOpenroads (Ord)
Reposted 5 Days AgoSaved
In-Office
San Jose, CA, USA
138K-206K Annually
Senior level
138K-206K Annually
Senior level
Semiconductor • Manufacturing
The role involves RTL design, validation, and development for memory and storage technologies, requiring collaboration with cross-functional teams on innovative solutions.
Top Skills: AxiCad Tools (SynopsysCadence Tools)CxlDdr4/5EthernetFpga Design ToolsMentorNvmePcieRtl DesignVerilog
Reposted 5 Days AgoSaved
In-Office
Malta, NY, USA
79K-146K Annually
Internship
79K-146K Annually
Internship
Semiconductor • Manufacturing
The role involves advancing 3D heterogeneous integration design through specifications, collaborations, and the development of test vehicles within a semiconductor manufacturing setting.
Top Skills: 3D Heterogeneous IntegrationDie-To-Wafer BondingEdaElectrical RulesTovTsvWafer-To-Wafer Bonding
Reposted 5 Days AgoSaved
In-Office
Melbourne, FL, USA
79K-148K Annually
Senior level
79K-148K Annually
Senior level
Aerospace • Logistics • Security • Software • Cybersecurity
Design primary and secondary metallic and composite aircraft structural parts and assemblies. Lead IPT design efforts, develop product definition packages, collaborate with analysis, manufacturing, and materials teams, employ GD&T and MBE, mentor junior engineers, and support fabrication and installation trade studies.
Top Skills: Gd&TModel Based EngineeringNx Solid ModellingTeamcenter
Reposted 5 Days AgoSaved
In-Office
Manhattan Beach, CA, USA
92K-138K Annually
Junior
92K-138K Annually
Junior
Aerospace • Logistics • Security • Software • Cybersecurity
Develop and maintain Process Design Kits (PDKs) and DRC/LVS flows across ADS, AWR, and Cadence; create mask layouts, scripts, and automated flows; support model and semiconductor device integration for compound microelectronics.
Top Skills: AdsAelAssuraAwrCadCadenceCalibrePdkSkill
Reposted 5 Days AgoSaved
In-Office
2 Locations
122K-195K Annually
Senior level
122K-195K Annually
Senior level
Software • Semiconductor • Manufacturing
Design and deliver high-quality SystemVerilog RTL for advanced process nodes (5nm and below). Perform PPA optimization, CDC/RDC analysis, low-power design, timing closure, and hand off to physical design. Collaborate with Architecture, Verification, and Physical Design teams and drive SoC integration for high-speed memory and SerDes protocols.
Top Skills: Clock Domain Crossing (Cdc)Ddr4Ddr5HbmLow-Power DesignLpddr5Lpddr6Ppa OptimizationReset Domain Crossing (Rdc)SerdesSocSystemverilogTiming Closure
Reposted 5 Days AgoSaved
In-Office
3 Locations
129K-207K Annually
Expert/Leader
129K-207K Annually
Expert/Leader
Software • Semiconductor • Manufacturing
Lead constrained-random verification of high-throughput Ethernet ASICs for AI/ML acceleration using SystemVerilog/UVM testbenches, drive coverage closure, run simulations with VCS/Incisive, script automation, collaborate with global design and architecture teams, and provide technical leadership.
Top Skills: IncisivePerlPythonSvaSystem VerilogUvmVcs
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