Top Design Engineer Jobs

Design Verification Engineer responsible for test planning, verification, debugging, adversarial testing, and writing verification environments using HVLs and methodologies (UVM/RVM/OVM). Works with RTL, assertions, code coverage, and simulation acceleration tools; strong communication and scripting skills required.

Design and implement production-grade backend services and platform APIs in Go. Build Kubernetes-native components (controllers, operators, CRDs, webhooks), integrate with CI/CD, observability, and security systems, and apply AI/agentic programming to automate platform workflows and improve developer productivity. Troubleshoot distributed systems and participate in architecture reviews.

Design, simulate, and verify RTL-based ASIC blocks for SoC products. Perform module design, synthesis, RTL/gate-level simulation, pre-/post-layout timing verification, static timing and cross-domain clocking analysis. Support FPGA/emulation bring-up, write detailed design specifications, and collaborate on high-speed data path and state-machine implementations.

Design and document low-voltage electrical hardware and system-level circuitry for medical equipment. Gather requirements, produce high-level and detailed designs, perform power/analog/digital interface design and simulation, create schematics, support PCB/layout and harness development, and transition designs to production while following regulatory and safety standards.

Develop and execute FPGA/ASIC RTL verification tests and test plans using SystemVerilog/UVM. Review designs and RTL, analyze failures, write bug reports, and work with IP vendors and design/firmware engineers to resolve issues.

Develop and extend verification methodology for MAC-layer unit simulations and SoC environments. Architect and implement testbenches, APIs, golden reference models, 802.11 protocol generators/checkers. Define metrics and implement tests for functional correctness, coverage, and performance. Collaborate across teams and use scripting and simulator tools for debug and validation.

Lead and manage electrical engineering design for NYC public school projects, overseeing teams, ensuring code and FDNY compliance, producing design and construction documents, managing submittals, site observations, stakeholder coordination, and implementing technical standards across program projects.

Verify complex hardware systems, including custom IP blocks and SoCs. Develop verification plans, testbenches, and maintain high coverage for reliable silicon.

As a Project Engineer, you will lead design efforts for gas distribution and transmission systems, mentoring junior engineers while ensuring compliance and technical accuracy on mid-sized projects.

The Design Criteria Engineer will develop design criteria for satellite systems, perform peer reviews, guide engineers, and track hardware readiness for launch. Responsibilities include risk mitigation and configuration management, along with process improvements in satellite design and manufacturing.

The Project Engineer III will mentor others, serve as a technical expert in power systems consulting, manage projects, and ensure safety practices. Responsible for scope, budget and schedule review, and providing innovative solutions in substation physical design.

The Staff Design Verification Engineer drives the verification of cache-coherent interconnect subsystems, focusing on CXL protocols and integration, defining verification plans, and improving overall verification quality through collaboration and mentorship.

The intern will join the Design Verification Infrastructure team to develop and maintain the Verification Platform, enhancing design verification technologies through collaboration and software development in Scala and Python.

The engineer designs analog and mixed-signal chips, manages layout processes, oversees verification plans, and runs complex simulations. Also responsible for guiding junior staff and consulting with users and vendors for alignment on project goals.

Lead verification strategy and execution for complex ASIC/SoC programs. Architect scalable UVM/SystemVerilog-based verification infrastructure, drive emulation/prototyping and formal verification, mentor teams, influence ASIC design for testability, and lead root-cause analysis during silicon bring-up and post-silicon validation.

Design and maintain block/cluster/top-level ASIC verification environments, build reusable testbenches, create and run constrained-random and directed tests, implement coverage, run gate-level simulations, support emulation and post-silicon bring-up, and collaborate with designers and software teams to debug complex chip issues.

Lead and define ASIC verification strategy and methodology across programs. Architect scalable verification infrastructure, mentor teams, drive cross-functional improvements, influence ASIC design for verifiability, and lead root-cause analysis during bring-up and post-silicon validation.

Design new products and features for the semiconductor industry, produce 3D models, support cross-functional engineering, and ensure reliable product function.

Provide technical leadership and design oversight for highway engineering projects. Develop design criteria, alignments, pavement, signing, MOT, utility coordination, specifications, quantities, estimates, and 3D models in OpenRoads. Perform technical reviews, coordinate with discipline leads and PMs, contribute to staffing and proposals, prepare technical presentations, and mentor staff to meet client scope, schedule, budget, and quality standards.

The role involves RTL design, validation, and development for memory and storage technologies, requiring collaboration with cross-functional teams on innovative solutions.

The role involves advancing 3D heterogeneous integration design through specifications, collaborations, and the development of test vehicles within a semiconductor manufacturing setting.

Design primary and secondary metallic and composite aircraft structural parts and assemblies. Lead IPT design efforts, develop product definition packages, collaborate with analysis, manufacturing, and materials teams, employ GD&T and MBE, mentor junior engineers, and support fabrication and installation trade studies.

Develop and maintain Process Design Kits (PDKs) and DRC/LVS flows across ADS, AWR, and Cadence; create mask layouts, scripts, and automated flows; support model and semiconductor device integration for compound microelectronics.

Design and deliver high-quality SystemVerilog RTL for advanced process nodes (5nm and below). Perform PPA optimization, CDC/RDC analysis, low-power design, timing closure, and hand off to physical design. Collaborate with Architecture, Verification, and Physical Design teams and drive SoC integration for high-speed memory and SerDes protocols.

Lead constrained-random verification of high-throughput Ethernet ASICs for AI/ML acceleration using SystemVerilog/UVM testbenches, drive coverage closure, run simulations with VCS/Incisive, script automation, collaborate with global design and architecture teams, and provide technical leadership.