Top Design Engineer Jobs

Design and maintain block, cluster, and top-level ASIC verification environments. Develop simulation models, test plans, directed and random tests, coverage metrics, and multi-chip simulations. Perform end-to-end verification, debug designs, collaborate with architects, designers, software teams and vendors, and support post-silicon bring-up and performance analysis.

Develop, deploy, and own RTL-to-GDSII physical design methodology and CAD flows for IP delivery. Automate PPA exploration, document flows, partner with design teams and EDA vendors, qualify new nodes/PDKs and EDA releases, and apply ML/LLMs where they improve flow optimization and scalability.

Ensure Falcon and Dragon flight hardware meets design criteria and reliability standards. Perform design reviews and test approvals, develop requirements and verification approaches, enable aircraft-like operations, drive design improvements with hardware teams, and build specialized design/analysis tools.

Develop and execute verification plans and environments for complex digital and mixed-signal IP. Create UVM testbenches, random and directed tests, assertions, functional models; perform coverage closure, debug RTL and gate-level failures, and collaborate with design teams and EDA vendors. May work with emulation and FPGA prototyping and adopt advanced verification flows.

Lead cross-disciplinary teams to design large-scale material handling systems: develop 3D models and proposals, generate bills of materials, validate vendor quotes, assess risks, apply value engineering, and own all engineering deliverables during the quotation phase to ensure smooth turnover to execution.

Lead design and development of analog and mixed-signal IP (amplifiers, comparators, data converters, references, monitors). Perform transistor-level schematic design, simulation, PVT and Monte Carlo analysis, collaborate with layout and SoC teams, support silicon bring-up and validation, and mentor junior engineers.

Lead development and execution of test plans and CONOPs for RF and cloud-enabled systems. Oversee instrumentation setup, demonstrations, field exercises, data collection and analysis, system deployment/configuration, and RF system testing across on-prem and cloud environments. Support BAST RAD portfolio with up to 25% travel and collaboration between Melbourne, FL and Space Park, CA.

Lead and execute design transfers from development through manufacturing and post-launch. Define system-level I&T requirements, develop test plans, identify and mitigate I&T and manufacturing risks, document best practices, and coordinate cross-functional multi-site teams. Support program planning, schedule/cost control, and customer/government interactions; travel occasionally.

Lead design and implementation of secure embedded controller and cryptographic ICs. Drive architecture, RTL development, verification, and bring-up. Support integration activities (lint, CDC, synthesis, DFT), work with physical design on STA/power/floorplanning, debug hardware/firmware interactions, and collaborate across global teams to deliver automotive, industrial, and security-focused ASIC/FPGA products.

Lead IO and pad ring planning for advanced SoC storage and memory controller designs. Create and validate pad ring DEFs, bump maps, IO netlists, and handoff deliverables. Coordinate with architecture, IP, packaging, implementation, foundry, and verification teams to ensure IO/package compliance, support silicon debug, and drive design improvements.

Design circuit board assemblies and system-level electronics, conduct design reviews, prepare documentation, provide technical support, and improve engineering practices.

Work with R&D and manufacturing teams to embed testability into product designs. Review schematics/layouts, develop DFT guidelines, estimate test coverage, support ICT/flying-probe/bed-of-nails test development (SPEA 4080, Keysight i3070), analyze test data, and champion DFT methods to ensure manufacturability and reliable production ramp.

Support full product lifecycle for aerospace electronic/electrical systems: requirements analysis, systems and hardware/software design, lab specification, integration and flight testing, supplier oversight, field support, and technology research to ensure designs meet functional requirements.

Lead end-to-end DFT/DFx strategy and hands-on implementation for AI inference ASICs: define DFT architecture, integrate into RTL and third-party IP, drive ATPG/BIST/scan verification through tapeout, partner with physical design and external vendors, and support silicon bring-up.

Design, develop, validate, and release cooling components for gas and electrified vehicles (hoses, tubes, heaters, valves, pumps, air induction). Collaborate cross-functionally, manage suppliers, create and maintain DVP&R and DFMEA, apply APQP and DFSS, use CAE for simulations, and utilize CATIA V5/NX, Vis Mockup, and TeamCenter to meet program milestones and quality standards.

Develop and execute verification plans and testbenches for interconnect and chassis IP; build reusable verification components, constrained-random tests, and debug infrastructure; perform simulation and formal verification, analyze failures, close bugs, plan functional coverage, and improve verification automation and regression quality.

The ASIC Design Efficiency Engineer will develop innovative hardware and system designs, focusing on performance, power, and area improvements, while collaborating with cross-functional teams.

Lead electrical subsystem design for aircraft including wiring and harness design, power generation/distribution, requirements, testing, data analysis, troubleshooting, supplier coordination, and verification to ensure airworthiness.

Design and analyze aircraft electrical subsystems including wiring, power generation, conversion and distribution. Create requirements, perform electrical loads analysis, test planning, lab testing, data processing, troubleshooting, supplier coordination, and verification to ensure airworthiness and compliance with aerospace standards.

Lead design, development, and release of ADAS components (radar, cameras, ultrasonic, ECUs). Manage suppliers/programs, track and resolve issues, author/approve FMEAs/DVPRs, develop validation and diagnostics plans, support launch and warranty, and coordinate cross-functional integration and risk mitigation.

Develop and execute verification plans and testbenches for analog/mixed-signal ICs. Run RTL and gate-level simulations, coverage regressions, automate regressions with scripts, track closure, and improve DV methodology while collaborating with design and systems teams to ensure first-pass silicon success.

Lead verification planning and execution for high-performance out-of-order CPU core blocks. Define verification strategy, develop robust UVM/SystemVerilog environments, write checkers/assertions, drive coverage closure, debug complex microarchitectural issues, and partner with architecture, RTL, performance, and software teams to raise verification quality and provide reusable methodology.

Lead verification planning and execution for high-performance out-of-order CPU core blocks. Define verification strategy, build testbenches, assertions, and coverage models, perform root-cause debug, work with architecture/RTL/performance teams, and drive verification closure and reusable methodology across core generations.

Lead functional verification for high-performance out-of-order CPU cores. Plan and execute block-to-core verification, develop UVM/SystemVerilog testbenches, write coverage and assertions, create constrained-random and directed tests, debug failures, collaborate with architects and RTL teams, and contribute reusable DV methodology and infrastructure to achieve signoff-quality verification.

Lead verification planning and execution for high-performance out-of-order CPU core blocks (frontend, midcore, LSU, prefetch). Define verification strategies, develop environments, assertions, scoreboards, stimulus and coverage models, perform root-cause debug, partner with architecture and design teams, and deliver reusable methodology to close microarchitectural risks and achieve signoff.