Top Design Engineer Jobs

Design and deliver high-quality SystemVerilog RTL for advanced process nodes (5nm and below). Perform PPA optimization, CDC/RDC analysis, low-power design, timing closure, and hand off to physical design. Collaborate with Architecture, Verification, and Physical Design teams and drive SoC integration for high-speed memory and SerDes protocols.

Lead constrained-random verification of high-throughput Ethernet ASICs for AI/ML acceleration using SystemVerilog/UVM testbenches, drive coverage closure, run simulations with VCS/Incisive, script automation, collaborate with global design and architecture teams, and provide technical leadership.

Manage and drive photonics layout and design automation, leading a team, ensuring quality, and facilitating cross-functional collaboration in a dynamic environment.

The role involves defining and implementing RTL for high-performance RISC-V CPUs, collaborating with various teams to ensure design meets functional, timing, and power goals while using innovative optimization techniques.

The Physical Design Engineer will lead efforts in solving physical design challenges, improve RTL-to-GDS methodologies, and integrate AI/ML solutions into CAD flows, focusing on performance and runtime improvements.

Lead and mature design quality for NPI hardware by driving DFM/DFA reviews, GD&T and tolerance analysis, DFMEA and DVP&R planning, change-control review, root-cause/CAPA, PPAP/first-article activities, design quality metrics, standards adoption, and mentorship to improve manufacturability and production readiness.

Lead mixed-signal pre-silicon verification activities: create verification plans, build simulation environments and behavioral models, run automated regressions, analyze results, participate in design reviews, and support post-silicon validation and correlation to ensure first-pass silicon success.

Own design, development, validation, and release of sunroof systems and components. Responsibilities include CAD modeling, DVPR testing, change and BOM management, prototype/production support, root-cause for field warranty issues, weight/cost reduction, and communicating technical status to management.

Design and verify mixed-signal current-sensing ICs across the full IC lifecycle: RTL design, synthesis, P&R, timing analysis, test development, mixed-signal verification, automation, and silicon bring-up to ensure first-pass success.

Design, develop, and optimize FPGA fabric architecture (interconnect, routing, logic, memory, clocking) using SPICE and Verilog. Collaborate with architects, verification, layout, timing, and software teams; create schematics, simulation models, documentation, and support silicon validation, verification, and timing characterization.

Build and ship polished production-quality UI (including mobile), craft layouts, typography, responsiveness, motion, and micro-interactions with Tailwind. Contribute components, tokens, and shared UI foundations. Implement interfaces using React, Next.js, and TypeScript, optimizing for performance, accessibility, and maintainability. Raise frontend craft via reviews and critiques while working closely with founders and customers.

Develop and implement verification strategies and reusable SystemVerilog/UVM testbenches; write tests, manage regressions, collect coverage, and debug issues across simulation, emulation, and silicon bring-up while collaborating with architects, RTL, firmware, and software teams.

Lead development and execution of verification strategies and reusable UVM/SystemVerilog testbenches. Implement tests, manage regressions, gather coverage, and debug issues across simulation, emulation, gate-level and silicon bring-up. Collaborate with architects, RTL, physical design, firmware, and validation to improve verification infrastructure and methodology.

Design and implement verification strategies and reusable SystemVerilog/UVM testbenches; create tests, run regressions, collect coverage, and debug across simulation, emulation, and silicon bring-up. Collaborate with architects, RTL, physical design, firmware, and validation teams while improving verification infrastructure and methodologies.

Design and build a scalable, responsive UI; lead frontend architecture and optimization; apply UI/UX best practices; integrate with backend APIs; ensure high web performance and deploy user-facing features.

Build and scale silicon design methodology, tooling, and abstractions to accelerate first-party chip development. Automate workflows, improve reproducibility and observability, partner with architects, RTL, verification, compiler and systems teams, and apply tools to construct complex SoCs while identifying design risks early.

Lead development of SystemVerilog/UVM verification environments for complex SoC and networking designs. Define verification strategy, create constrained-random and coverage-driven tests, develop BFM/monitors, debug failures, automate regressions with Python/Perl/C++, and mentor junior engineers to meet tape-out schedules.

Design and develop digital and analog circuits for mixed-signal embedded systems, focusing on circuits powered from AC mains, ensuring compliance with safety standards and troubleshooting during production.

Lead design and delivery of SMAC workflow methodology and infrastructure to keep system specifications and manufacturing test specs aligned. Build production-grade Python pipelines, automated checks, CI gates, and agent-ready tooling that detect spec drift pre-silicon. Integrate workflows into program milestones, drive cross-org adoption across design, operations, and DFX, and apply AI where appropriate while ensuring reviewable, auditable artifacts.

Design, analyze, and deliver industrial power transmission products. Develop new solutions, produce engineering designs and bills of materials, support manufacturing and customers, collaborate cross-functionally, ensure compliance with standards, and communicate technical status, risks, and outcomes.

Hands-on principal engineer driving physical implementation, timing closure, and physical verification for analog and mixed-signal IP. Owns Fusion Compiler APR flows, floorplanning, placement, routing, ECOs, timing debug, and signoff readiness while coordinating cross-functional teams and mentoring engineers.

Lead and own verification of fabric interconnect components: define verification strategies and test plans, develop formal verification environments, run and debug simulations, improve verification efficiency and tools, apply generative AI to verification, and coach/mentor teammates.

Design, develop, and support fluid and mechanical systems for rocket test facilities across the lifecycle. Produce P&IDs, models, drawings, and analyses; apply fluid mechanics and structural fundamentals for cryogenic, propellant, and high-pressure gas systems; support hazard assessments, supplier coordination, fabrication, installation, commissioning, and configuration management.

Apply deep design expertise and BIM execution to independently design and deliver complex building projects. Develop and coordinate multidisciplinary Revit BIM models, evaluate code compliance and constructability, and translate engineering judgment into AI-enabled workflows. Collaborate with AI researchers and engineers to improve model generation, validation, and documentation, and support client engagements.

Develop and implement complex ASIC verification environments and test plans for high-performance network switch ASICs/FPGAs. Collaborate with architects and design teams, perform simulations, and drive verification to closure through tape-out and production-ready delivery.