Top Senior Hardware Engineer Jobs in Sacramento, CA

Develop and maintain transistor-level timing characterization flows, CAD infrastructure, and automation for custom IPs and memory. Collaborate with circuit, memory, STA, and methodology teams; validate Liberty models and SPICE-based characterizations; support platforms, scripts, and EDA vendor tool evaluations.

Develop and maintain full-chip physical implementation flows for SoC designs, including floorplanning, partitioning, hierarchical block integration, placement and routing coordination, power grid planning and IR analysis, CTS strategy integration, and scalable multi-block/multi-power-domain assembly methodologies using Innovus.

Lead standardization strategy for optical transport and Ethernet technologies, develop and advocate contributions to standards bodies (ITU‑T, IEEE, OIF, OpenROADM), coordinate with PLMs and R&D, report progress internally, provide technical influence and guidance, and represent Nokia at standards meetings and industry events.

Lead end-to-end hardware design for high-speed Ethernet switches: author specs, select components, capture schematics, collaborate on PCB layout and SI/PI simulations, specify stackups, work with contract manufacturers, perform lab bring-up and complex system debug with software/test teams, drive DFM for production, and mentor junior engineers.

The role involves optimizing hardware support within a software stack for AI model deployment, collaborating with teams and hardware vendors to enhance performance and portability across platforms.

The Principal Hardware Engineer will lead the design of hardware systems for a satellite communications platform, focusing on power distribution, signal integrity, and PCB design, while ensuring high-reliability and fault tolerance in space environments.

The role involves managing hardware product quality issues, leading root cause analysis, driving corrective actions, and collaborating with various teams to improve product quality and reliability.

Design, build, and operate reliable backend systems while mentoring engineers, participating in design discussions, and improving system performance.

Design and verify mixed-signal layouts in sub-micron CMOS technologies, collaborating with ASIC engineers to ensure integration in VLSI products.

As a Senior Hardware Engineer, you'll drive DPU integration into server platforms, execute validation testing, and develop automation for data analysis while collaborating with cross-functional teams and vendors.

The role involves physical layout design for high-speed mixed-signal circuits, collaborating with cross-functional teams, and utilizing various design and verification tools.

Lead reliability strategy and environmental validation for satellite user terminal hardware. Design and run HALT/HASS/ESS tests, oversee weatherproofing and thermal/vibration testing, perform failure analysis (X-ray, microscopy, cross-sectioning), own DFMEA and physics-of-failure models to predict MTBF and warranty risk, collaborate with electrical and mechanical teams and external labs to drive hardware improvements and regulatory compliance.

Lead on-site technical authority for datacenter hardware reliability and fleet health. Troubleshoot complex hardware failures, drive root cause analysis and corrective actions, coordinate with vendors and cloud providers, establish maintenance standards and runbooks, support new hardware introductions and spare parts strategy, mentor technicians, and analyze failure trends to improve reliability across large-scale GPU and server deployments.

The Senior Package Layout Engineer will collaborate with teams to design IC substrates, optimize layouts, and improve productivity using Cadence tools.