Top Senior Hardware Engineer Jobs in Sacramento, CA

Lead complex hardware designs for high‑performance networking platforms across the full lifecycle: component selection, schematic capture, board architecture, bring‑up, debug, validation, and system‑level analysis. Drive high‑speed digital and power integrity decisions, perform root‑cause analysis and empirical testing, mentor junior engineers, and collaborate with cross‑functional teams to deliver production‑ready designs.

Develop and maintain full-chip physical implementation flows for SoC designs, including floorplanning, partitioning, hierarchical block integration, placement and routing coordination, power grid planning and IR analysis, CTS strategy integration, and scalable multi-block/multi-power-domain assembly methodologies using Innovus.

Pipeline hiring for hardware engineers at all experience levels. Work includes circuit board design, schematic capture, component selection and prototype bring-up, hardware debug/testing and failure analysis, integration with firmware/software teams, and design for manufacturability with production handoff.

Design and develop system power hardware for next-generation networking platforms, from component selection and schematic design through board bring-up, debugging, validation, testing, margin analysis, and root-cause analysis. Collaborate with cross-functional teams to ensure robust, manufacturable, high-performance power delivery.

Lead end-to-end hardware design for high-speed Ethernet switches: author specs, select components, capture schematics, collaborate on PCB layout and SI/PI simulations, specify stackups, work with contract manufacturers, perform lab bring-up and complex system debug with software/test teams, drive DFM for production, and mentor junior engineers.

The Principal Hardware Engineer will lead the design of hardware systems for a satellite communications platform, focusing on power distribution, signal integrity, and PCB design, while ensuring high-reliability and fault tolerance in space environments.

Lead standardization strategy for optical transport and Ethernet technologies, develop and advocate contributions to standards bodies (ITU‑T, IEEE, OIF, OpenROADM), coordinate with PLMs and R&D, report progress internally, provide technical influence and guidance, and represent Nokia at standards meetings and industry events.

Design, build, and operate reliable backend systems while mentoring engineers, participating in design discussions, and improving system performance.

Design, test, and validate next-generation server hardware and components for performance, power, and reliability. Diagnose and resolve hardware issues across engineering and manufacturing, document results, and develop/maintain test scripts. Collaborate with internal teams and OEM/ODM partners to scale platforms for global deployment.

The Senior Package Layout Engineer will collaborate with teams to design IC substrates, optimize layouts, and improve productivity using Cadence tools.

The role involves optimizing hardware support within a software stack for AI model deployment, collaborating with teams and hardware vendors to enhance performance and portability across platforms.

The role involves managing hardware product quality issues, leading root cause analysis, driving corrective actions, and collaborating with various teams to improve product quality and reliability.