Top Design Engineer Jobs

The role involves architecting scalable verification solutions for HBM products, driving verification strategies, engaging with customers, and mentoring engineers.

Own functional verification of high-speed SerDes and PHY IP for AI connectivity platforms. Architect UVM environments, define coverage and sign-off strategies, develop SystemVerilog testbenches, verify equalization, CDR, training, and link bring-up, and drive coverage closure through tape-out. Collaborate with analog, digital, SoC, firmware, post-silicon, and customer teams on AMS co-simulation, RNM, emulation, and protocol compliance. Mentor junior engineers and lead verification methodology and IP reuse improvements.

Design, implement, optimize, verify, and debug complex FPGA solutions using RTL, simulation, and advanced testbenches. Collaborate on board-level interfaces, high-speed protocols, RF DSP, hardware integration, and system architecture. Document designs, support project milestones, improve development processes, interface with customers, and mentor junior engineers. Work cross-functionally with software, mechanical, hardware, and systems teams to deliver FPGA-based products.

Design and modify electrical wire harness layouts for off-highway equipment using Creo Cabling. Manage small harness projects, coordinate with manufacturing, quality, suppliers and other design teams, pull parts in PTC Windchill/SAP, review 2D harness drawings, and participate in cross-functional design reviews.

Design and validate antennas and RF front-ends from simulation to production: EM simulation, PCB RF schematic/layout, RF measurements (VNA, S‑parameters, radiation patterns), multi-radio coexistence, production qualification, and documentation.

Remote 12-month contract RTL Design Engineer to own micro-architecture and RTL implementation for complex digital blocks. Requires SystemVerilog/Verilog expertise, memory controller and SoC integration experience, IP integration, multi-clock-domain design, and sign-off familiarity (CDC/RDC/lint/synthesis). Works independently and collaborates with DV for closure and debug.

Lead architecture, design, integration, validation, and production of highly integrated multi-radio RF front-end systems for aircraft and ground platforms. Define RF architectures supporting LTE/5G, GNSS, Wi‑Fi, ADS‑B/UAT, Bluetooth, ISM, V2V; perform RF system analysis, coexistence mitigation, antenna-sharing and MIMO strategies; develop lab validation and production test methods; support certifications and supplier/manufacturer integration; mentor engineers and establish RF design standards and roadmaps.

Perform full-chip and block-level physical design: floorplanning, P&R, clock-tree synthesis, timing closure/STA, low-power implementation, power integrity and IR-drop, and physical verification to take hardmacros from netlist to GDS using industry EDA tools.

Perform physical implementation (place-and-route) and P&R experiments for Adreno GPU cores, including floorplanning, macro placement, CTS, routing, timing closure, STA, low-power (UPF/CPF) flows, physical verification (Calibre DRC/LVS/ERC), and automation scripting to validate new flows and methodologies.

Design and verify microarchitecture and RTL for high-speed PHYs and datapaths. Perform timing closure, timing constraints, PTSI, DFT insertion, and STA. Build HVL-based testbenches, linting and synthesis flows, and work with high-speed IO blocks (PLLs, DLLs, LDOs). Apply low-power techniques and collaborate across distributed teams.

Design and implement RTL and system-level SoC modules, perform logic synthesis and timing analysis, integrate modules into SOC, collaborate with architects and verification teams, support silicon bring-up, and improve design flows and methodologies to enhance efficiency and chip yield.

Support new product development and manufacturing scale-up for ALD, PVD, and PECVD coatings. Develop and optimize coating processes, design tooling and fixtures using SolidWorks, create drawings/BOMs/work instructions, support prototyping and validation, troubleshoot manufacturing issues, collaborate cross-functionally, work with suppliers, and ensure compliance with SAP/ETQ/EPDM/Accolade and quality systems.

Hands-on role designing, modeling, prototyping, testing, and implementing precision motion systems for semiconductor equipment. Perform FEA, structural dynamics, vibration and thermal analysis, create detailed CAD models and drawings, build and refine prototypes, and collaborate with systems, controls, manufacturing, and physics teams to drive design decisions and product implementation.

Designs, develops, and tests analog and digital circuitry, cable assemblies, data acquisition and electronic control systems for ship and submarine launch control. Performs troubleshooting of electromechanical systems, custom test setup design, EMI mitigation, and supports PCB/CCB and FPGA-related work. Requires US citizenship and ability to obtain Secret clearance. Position based in Sunnyvale, CA with ~10% travel.

Develop and lead verification strategies for AI inference ASICs, including SystemVerilog UVM environments, simulation testbenches, directed and constrained-random testing, coverage closure, debugging, and root-cause analysis. Collaborate with design, architecture, software, FPGA, and emulation teams across pre-silicon and post-silicon validation. Manage verification schedules, deliverables, and risk mitigation while helping ensure functional correctness and performance.

Develops and validates intelligent Autodesk Inventor models, configurable assemblies, reusable templates, metadata, and automation rules for structural steel engineering. Translates engineering standards and customer requirements into scalable workflows while improving design consistency, BOM and BOO creation, manufacturing readiness, and downstream data quality. The role supports standards catalog governance, model-based engineering, validation processes, and cross-functional collaboration with engineering, detailing, manufacturing, ERP, MES, and data teams.

Lead physical implementation of custom IP and SoC from RTL through GDSII. Execute synthesis, floorplanning, place-and-route, CTS, STA, power, reliability and physical verification. Analyze signoff results, resolve violations, optimize PPA, and develop/automate physical design methodologies while collaborating with RTL, DFT, timing, verification, and CAD teams.

Implement full-chip and block-level physical design for custom IP and SoC from RTL through GDSII. Execute synthesis, floorplanning, place-and-route, CTS, STA, physical verification and signoff. Optimize power, timing, congestion, and PPA, support DFT integration, root-cause issues, automate flows, and mentor junior engineers across multidisciplinary teams.

Leads control system hardware and software design, development, integration, testing, factory acceptance testing, installation, startup, and commissioning. Troubleshoots electrical and mechanical systems, interprets P&IDs and wiring diagrams, specifies instrumentation, supports HMI and PLC applications, and contributes to IT and network design for control integrations. Manages project tasks or small to mid-sized projects, communicates with customers, follows site standards, and may participate in on-call rotations and overnight travel.

Develop and execute system validation plans for semiconductor power-management products. Perform laboratory testing, electrical characterization, silicon bring-up, hardware debugging, root-cause analysis, and reliability validation. Build test fixtures and automated solutions using Python or LabVIEW, analyze data, document results, and collaborate with design, product engineering, applications, firmware, and ATE teams to resolve issues and support product release.

Design and microarchitect power-management, reset, and clocking subsystems for high-performance CPU and SoC IP. Specify architectures, implement RTL, perform sandbox verification, collaborate with verification, physical implementation, and software teams to meet frequency, area, and power goals.

Design and microarchitect power management, clocking, and reset solutions for RISC-V CPU and SoC IP. Define requirements, implement RTL, collaborate on verification, physical implementation, and software enablement to meet frequency, area, and power goals.

Design and microarchitect power-management, reset, and clocking solutions for high-performance CPU and SoC IP. Develop RTL, spec microarchitecture, run sandbox verification, collaborate with verification, physical implementation, and software teams to optimize frequency, area, and power and drive designs through tapeout.

Implement and manage long-distance and local network infrastructure, telemetry and alarming platforms; provision, install, groom, roll, decommission network elements; research and reconcile provisioning database records; validate engineering per project specs; coordinate with NOC/field to verify readiness and resolve data integrity or outage issues.

Design and optimize regional cellular RF networks (CRAN, macros, small cells) balancing capacity, coverage, and cost. Create search areas, cell translations, perform drive testing, prepare FCC/FAA/FAS submissions, support site acquisition, and work with performance teams to reduce lost calls. Require knowledge of CDMA, LTE/VoLTE, link budgets, RF prediction tools, and vendor RAN systems like Ericsson. Proficiency in Siterra/MapInfo and Office applications preferred.