Top Design Engineer Jobs

Define NTN RAN requirements for a LEO satellite constellation, support link budget and air-interface capacity studies, participate in vendor evaluation and selection, define bearer services, collaborate with developer partners and product management, and support 3GPP-based SATCOM system development and testing.

The Systems Engineer will own the spacecraft simulation toolchain for Vast, focusing on supporting design and analysis for spacecraft systems, ensuring rigorous validation and collaboration across disciplines.

Responsibilities include contributing to verification methodology, creating testbenches for silicon validation, and driving reviews on verification progress.

Responsible for ensuring compliance with quality assurance procedures, conducting audits, supporting product development, and authoring documentation, among other duties.

Lead cross-functional teams to define and evolve DFM rules and methodologies for advanced logic nodes. Translate silicon learning into actionable design feedback, develop and optimize yield tools and flows, manage design rule validation and waivers, drive scribe line layouts, and support foundry customers to accelerate yield improvement and ramp speed.

The Photonic Design Automation Engineer will develop and scale the layout-to-netlist flow for silicon photonics, ensuring accurate model extraction and automation for reliable IC tape-outs. Responsibilities include netlist generation, automation pipelines, and collaboration across teams.

This role involves designing complex electrical systems, including FPGA circuits and power supply topologies, collaborating with cross-functional teams, and overseeing product transitions from prototype to production.

Lead design control and risk management activities for new and sustaining medical device products. Support verification/validation, usability studies, process qualifications, audits, and QMS updates while training staff and ensuring compliance with regulatory standards.

Design and architect digital subsystems for low-power IoT SoCs, implement RTL (SystemVerilog/Verilog), create testbenches and stimulus, manage multi-clock/power domains and timing closure, integrate security features (TrustZone, Secure Boot, PSA L2), and collaborate cross-functionally to deliver silicon to high-volume production.

Lead CAD/EDA engineering support for digital and analog teams: maintain and improve EDA environments, develop automation and workflows, troubleshoot tools and infrastructure, manage compute/license resources, coordinate vendors and contractors, and drive CAD methodology and roadmap improvements across the silicon lifecycle.

Lead design, development, validation, and release of EV cooling components. Create and manage DVP&R and DFMEA, run CAE simulations, apply APQP and DFSS, manage suppliers, and coordinate cross-functional integration to meet program milestones.

Build and maintain an accessible design system (Expedite), shipping production-ready React/TypeScript components and tokens. Define AI-assisted design-to-code workflows, create LLM guidelines, train teams, establish governance and WCAG AA compliance, and drive adoption across web and mobile.

Design, implement, verify, and tape-out analog power ICs (PMICs). Collaborate with system, characterization, modeling, and layout teams; define architectures, guide physical design, validate in lab, and develop DFT and production test plans to meet performance and production requirements.

Serve as the technical expert in GD&T and functional gage design to ensure parts are measurable and inspectable. Design, review, and improve custom gauges, fixtures, and tooling; interpret drawings against ASME Y14.5/Y14.43; provide inspection feasibility and disposition guidance; partner with engineering, quality, manufacturing, and suppliers to improve dimensional quality and manufacturability; deliver technical training and support drawing review and release workflows. Onsite in Salt Lake City, UT.

Lead verification of custom ASIC/SoC from block to full-chip: develop verification plans, build SystemVerilog/UVM testbenches, run constrained-random and directed tests, use SVA and formal methods, manage regressions and CI, drive coverage closure, support post-silicon bring-up, and influence DV methodology across cross-functional teams.

The Senior Design Verification Engineer develops and verifies silicon IP, optimizing and characterizing performance using advanced tools, while leading a team.

Debug and root-cause production hardware issues across CPU/ASIC, power, SI, clocking, PCIe, optics and components. Perform lab measurements, collaborate with software, manufacturing, and component teams, write debug scripts, implement fixes in firmware/schematics/BOM/fab, identify test escapes, and present RCA to executives and customers.

Lead configuration and CAD management for a reentry system: integrate structural, mechanical, fluids, and avionics subsystems; define interfaces; drive manufacturable designs; manage vehicle CAD models and change control; support requirements, verification planning, and cross-functional configuration reviews to meet program milestones.

Hands-on Mechanical Engineering intern to design, build, and test robot subsystems. Responsibilities include CAD in NX, mechanism design and analysis, prototype manufacturing, fixture fabrication, test plan creation, troubleshooting, and documentation to support fabrication and assembly over a 3-month Fall internship.

Design and own core Python-based verification infrastructure: declarative build graph, run-record store, simulator backends, failure bundles, CI/grid integrations, and operational deployment; support AI agents with deterministic guardrails and provide docs and rollout support to DV teams.

The Senior Technical Documentation Engineer ensures compliance with documentation practices, updates R&D procedures, manages design control documentation, and supports documentation efforts throughout product development.

Design, implement, verify, and document micro-architecture and RTL for complex power-management ASICs. Own end-to-end development from architecture and RTL coding to synthesis, timing closure, formal and gate-level verification, silicon bring-up, documentation, and cross-functional reviews while improving design and verification methodologies.

Lead and define design verification strategy for semiconductor IP/SoC, develop and execute verification plans and testbenches, debug RTL and silicon issues, mentor engineers, and collaborate with cross-functional teams to ensure product quality and delivery.

Lead verification architecture, execution, emulation and post-silicon validation for next-generation ASICs. Drive verification methodologies, lab bring-up, emulation toward successful tapeout, and lead cross-functional ASIC development teams.

Lead creation of complex pre-silicon and post-silicon verification environments and tests for AI accelerators. Define verification plans, develop testbenches (SystemVerilog/UVM), debug simulation/emulation, implement coverage and scoreboards, and build scalable verification tooling and scripts while collaborating across hardware, firmware, and architecture teams.