Mirafra is a global product engineering services company with expertise in semiconductor design, embedded and application software.
Job Overview:
The Graphics team is looking for Experienced Physical Design Engineers to work on Adreno Graphics cores in the area of Physical Implementation.
Responsibilities:
The Physical Implementation Engineer will work in Qualcomms Adreno GPU team and will be responsible for all the P&R experiments targeted at validating new flows/methodologies.
Minimum Qualifications:
Able to deal with MSM Top level complexity from FP, Placement, CTS, Routing and timing closure Must be
able to take the Hardmacro through P&R from Netlist to GDS including timing closure, formal and Physical verification.
Tools: EDA Physical design tools experience ( Examples: Cadence Innovas, Synopsys ICC2, PrimetimeSi/Calibre/ etc)
Skills:
Physical design implementation expertize in latest technology nodes in one of the below domains or all of these.
1.Floor planning at Full chip level or Macro or Block Level
a.Macro placement, power grid implementation, power routing, special routing like analog signals etc
b.Power collapse/Low power implementation flow
2.P&R:
Place and route at chip level or block level, perform placement, timing closure in P&R mode, perform clock tree synthesis , routing etc
3.Timing closure/STA
a.Perform STA using primetime Si or Tempus or any industry standard STA engine, timing closure, ECO generation, timing correlation
b.Deep understanding of timing skills to perform correlation, timing fixes , corner/voltage definetions etc
4.Clock Tree Synthesis:
a.Perform custom or regular clock tree implementation at block level or top level.
b.Clock tree balance of complicated tree, clock power reduction techniques etc
5.Low Power Implementation
a.Power collapse/power gaing techniques/implementation
b.UPF/CPF flow knowledge
c.CLP/FV
6. Physical Verification Using Calibre a.Running all the PV checks (DRc/LVS/ERC/Softcheck ) and deep understanding of all the rules and fixes
7. Perl/Python/Shell script experience is also preferred to help with automation
All your information will be kept confidential according to EEO guidelines.
Skills Required
- Experience with place-and-route (P&R) from netlist to GDS including timing closure, formal and physical verification
- Ability to handle top-level SoC complexity including floorplanning, placement, CTS, routing and timing closure
- Experience with EDA physical design tools (Cadence Innovus, Synopsys ICC2)
- Static timing analysis (STA) expertise using PrimeTime Si, Tempus, or equivalent; timing closure and ECO generation
- Clock tree synthesis (CTS) experience at block and top level, including clock balancing and power reduction techniques
- Low-power implementation experience (power collapse handling, UPF/CPF flows, low-power techniques)
- Physical verification experience using Calibre and running DRC/LVS/ERC/soft checks and fixes
- Floorplanning experience at full-chip, macro, or block level including macro placement and power grid implementation
- Experience with power routing, special routing (analog), and power-collapse related flows
- Experience with timing correlation, corner/voltage definitions, and timing fixes
- Perl, Python, or Shell scripting for automation
What We Do
Mirafra Technologies, is a technology consulting company with focus on semiconductor Design Services, Embedded Software Development and Digital Transformation. Mirafra has a strong team of more than a 1000 engineers. We are headquartered in Bangalore with offices at Hyderabad, Chennai & Pune. We have offices in US and currently have 30 people working across North America. We also have operations in Singapore and Sweden. Mirafra engineers have delivered hundreds of successful projects and have repeatedly demonstrated an ability to solve the toughest problems. We invest in hiring the best engineers and then provide them with continuous training and development opportunities. Mirafra prides itself on having long and continuous engagements with its customers. We have more than 20 engagements which have been going on for more than 4 years each, with 4 of them for more than 8 years. Our customers range from startups to the top 10 semiconductor companies
