Top Design Engineer Jobs

Responsible for designing and testing high-power RF amplifiers for defense applications, including simulation, PCB layout, and integration of components.

The RF Microwave Design Engineer designs microwave components and systems, evaluates devices, and supports assemblies operating from DC to 60GHz for military and space programs.

The Mechanical Design Engineer will create mechanical designs, develop drawings, collaborate with teams, and optimize solutions using CAD software.

The Senior Mechanical Design Engineer will develop mechanical designs, lead reviews, optimize solutions, and ensure product integrity through testing and validation in collaboration with cross-functional teams.

Drive the design and development of high-power InP-based semiconductor lasers for high-speed data communication applications, ensuring technical leadership, hands-on device development, and collaborative coordination.

The Design Verification Engineer is responsible for verifying networking ASIC designs, developing test plans, implementing test suites, and ensuring completion through various metrics.

Lead chip-level digital architecture, own top-level RTL and integration, drive timing/CDC constraints and front-end flows, coordinate cross-discipline teams through tape-out, and mentor engineers while supporting post-silicon bring-up and validation.

Lead design and implementation of DSP algorithms in FPGA hardware, develop RTL with timing closure and resource optimization, integrate FPGA with Linux-based software using C/C++, test RF communication subsystems, and document system-level designs and integrations.

The Senior ASIC Design Engineer will design and implement RTL, analyze trade-offs, and collaborate on micro-architecture for GPUs and SoCs.

Design and develop RF and RF/optical hardware for defense and commercial systems, apply electromagnetics principles, and integrate computational analytics, ML/AI, and algorithm acceleration within agile prototyping and low-rate production workflows to transition technologies to customers.

The ASIC Physical Design Engineer will design, test, and deploy hardware, owning physical design flows end-to-end and collaborating across teams. The role emphasizes a strong understanding of both physical design and RTL, with an interest in improving design processes through software engineering.

As a Senior Chiplet Physical Design Engineer, you'll design and integrate chiplets into a System-in-Package, focusing on synthesis and place-and-route, while collaborating with global teams.

Lead micro‑architecture and RTL development for high‑performance connectivity ASICs. Define SoC specs, implement SystemVerilog RTL, drive front‑end flows (lint/CDC/synthesis/STA), support timing closure and PNR, collaborate on verification, pre‑ and post‑silicon validation, and mentor cross‑functional teams to deliver tape‑out ready designs.

Lead the frontend digital design of D2D PHY for chiplet systems, optimizing performance and collaborating across teams while mentoring junior designers.

Develop and maintain Intel’s asynchronous EDA design automation flow for neuromorphic silicon. Build algorithms, tools, utilities, scripts, and regression tests supporting RTL, verification, physical design, simulation, FPGA emulation, synthesis, and implementation. Create scalable frameworks for early software development and optimize custom low-power, high-performance designs. The role requires full ASIC lifecycle knowledge, multiple tape-outs, strong scripting skills, and experience using AI-assisted engineering tools.

Lead RTL micro-architecture and implementation for advanced ASICs from concept to silicon. Develop and debug complex RTL, integrate IP, support front-end flows (lint/CDC/synthesis/ECO), collaborate with verification/STA/physical teams, and build automation and AI-assisted tools to improve productivity and quality.

Design and validate electrical subsystems for ruggedized, mass-produced devices. Responsibilities include schematic capture, constraint-driven PCB layout, embedded communications, sensor integration, hardware bring-up, validation, debugging, and ensuring signal integrity, reliability, manufacturability, and compact form factors. The engineer collaborates with systems, RF, and software teams, owns EE deliverables, and leads hardware design efforts independently from initial design through production integration.

Characterize and optimize CMOS image sensor performance by bringing up new silicon, validating functionality, developing testing methodologies, analyzing pixel-level and analog/digital subsystems, and identifying improvements. Collaborate with design, process, applications, production, and quality teams to resolve system issues and support product transitions, yield, reliability, and quality goals.

Characterize and optimize CMOS image sensor performance by bringing up new silicon, validating functionality, developing testing methodologies, analyzing pixel-level and analog/digital subsystems, and identifying improvements. Collaborate with design, process, applications, production, and quality teams to resolve system issues, yield and reliability problems, and transition new products into production.

Design HVAC, plumbing, process utility, and mechanical systems for biopharmaceutical and biotech manufacturing facilities, including cleanrooms. Prepare drawings, specifications, calculations, equipment schedules, and utility documentation; coordinate with architects and other engineering disciplines; support code compliance and construction administration; manage mechanical scopes across concurrent projects; contribute to quality processes and mentor entry-level staff.

Design HVAC, plumbing, process utility, and mechanical systems for biopharmaceutical and biotech manufacturing facilities, including cleanrooms. Prepare drawings, specifications, calculations, equipment schedules, and utility documentation; coordinate with multidisciplinary teams; support code compliance and construction administration; manage mechanical scopes across projects; contribute to quality processes and mentor entry-level staff.

Designs, verifies, documents, and debugs complex FPGA-based digital systems using SoCs, embedded processing, high-speed interfaces, and custom IP. Translates system requirements into FPGA specifications, develops synthesizable SystemVerilog and verification IP, creates test strategies, integrates Xilinx AXI-based designs, and supports defect resolution. The role also drives design-quality practices and continuous improvement across long-term projects.

The role involves architecting scalable verification solutions for HBM products, driving verification strategies, engaging with customers, and mentoring engineers.

Own functional verification of high-speed SerDes and PHY IP for AI connectivity platforms. Architect UVM environments, define coverage and sign-off strategies, develop SystemVerilog testbenches, verify equalization, CDR, training, and link bring-up, and drive coverage closure through tape-out. Collaborate with analog, digital, SoC, firmware, post-silicon, and customer teams on AMS co-simulation, RNM, emulation, and protocol compliance. Mentor junior engineers and lead verification methodology and IP reuse improvements.

Design, implement, optimize, verify, and debug complex FPGA solutions using RTL, simulation, and advanced testbenches. Collaborate on board-level interfaces, high-speed protocols, RF DSP, hardware integration, and system architecture. Document designs, support project milestones, improve development processes, interface with customers, and mentor junior engineers. Work cross-functionally with software, mechanical, hardware, and systems teams to deliver FPGA-based products.