Top Design Engineer Jobs

Reposted 19 Days AgoSaved
In-Office
Santa Clara, CA, USA
159K-238K Annually
Senior level
159K-238K Annually
Senior level
Artificial Intelligence • Automotive • Semiconductor
As a Design Verification Engineer, you will verify chip designs, develop test plans, and lead teams on verification projects, ensuring high-speed data transfer meets specifications.
Top Skills: Arm AssemblyC++Eda Verification ToolsLinuxPerlPythonSystem VerilogUvm
Reposted 20 Days AgoSaved
In-Office
Santa Clara, CA, USA
172K-236K Annually
Expert/Leader
172K-236K Annually
Expert/Leader
Artificial Intelligence • Semiconductor • Manufacturing
Manage engineering teams to develop and characterize hardware technologies, resolve complex process issues, validate performance, and support cross-functional integration for advanced semiconductor and display manufacturing solutions.
Top Skills: Autocad
Reposted 20 Days AgoSaved
In-Office
2 Locations
164K-312K Annually
Senior level
164K-312K Annually
Senior level
Artificial Intelligence • Cloud • Information Technology • Software
The Physical Design Timing Engineer will perform SOC level timing analysis, ensuring designs meet performance and functionality requirements, collaborating with various teams to optimize solutions.
Top Skills: Clock Network DesignPhysical Design ToolsStatic Timing AnalysisSystem-On-Chip (Soc)Tcl ScriptingTiming Extraction Tools
Reposted 20 Days AgoSaved
In-Office
Santa Clara, CA, USA
175K-261K Annually
Senior level
175K-261K Annually
Senior level
Artificial Intelligence • Automotive • Semiconductor
Design high-performance analog circuits including PLL and SerDes blocks, lead projects, verify systems, and manage documentation and communication within the team.
Top Skills: AdeAnalog Circuit DesignDigital Signal ProcessingSpectreVirtuoso
Reposted 20 Days AgoSaved
In-Office
Westborough, MA, USA
109K-161K Annually
Junior
109K-161K Annually
Junior
Artificial Intelligence • Automotive • Semiconductor
The Design for Test Engineer assists in developing testability features for digital circuits, focusing on DFT structures and collaboration for product quality.
Top Skills: Digital Logic DesignEda ToolsHdl Languages (VerilogPythonShellTclVhdl)
Reposted 20 Days AgoSaved
In-Office
Austin, TX, USA
150K-275K Annually
Mid level
150K-275K Annually
Mid level
Artificial Intelligence • Hardware • Software
As a Design Verification Engineer, you will create and maintain UVM/SystemVerilog testbenches, execute verification plans, debug issues, and collaborate with cross-functional teams to ensure IP functionality and performance.
Top Skills: PerlPythonSystemverilogTclUvm
Reposted 20 Days AgoSaved
In-Office
Austin, TX, USA
150K-275K Annually
Mid level
150K-275K Annually
Mid level
Artificial Intelligence • Hardware • Software
As a Design Verification Engineer, you will collaborate with architects and RTL designers to verify designs, develop test plans and infrastructure, ensure performance, and debug issues across the hardware-software stack.
Top Skills: PythonSystemverilog
Reposted 20 Days AgoSaved
In-Office
Austin, TX, USA
150K-275K Annually
Senior level
150K-275K Annually
Senior level
Artificial Intelligence • Hardware • Software
The Design Verification Engineer will lead IP subsystem verification, develop UVM/SystemVerilog environments, and collaborate with cross-functional teams to validate hardware-software performance.
Top Skills: AmbaArcArmAxiEthernetPcieSystemverilogUvm
Reposted 20 Days AgoSaved
In-Office
Durham, NC, USA
135K-311K Annually
Senior level
135K-311K Annually
Senior level
Artificial Intelligence • Cloud • Information Technology • Consulting
The role involves leading VLSI design projects, providing technical expertise, reviewing designs for compliance, mentoring staff, and innovating within design teams.
Top Skills: Digital LogicEdaFpgaHardware Description LanguageProgramming And ScriptingVlsi
Reposted 20 Days AgoSaved
In-Office
Fort Lauderdale, FL, USA
Senior level
Senior level
Financial Services
The Senior Platform Engineer will design automated solutions, support deployments, implement management tools, and enhance system performance and security in a hybrid role.
Top Skills: AnsibleAWSAzureBashChefDockerElasticsearchGitlabGoogle Cloud PlatformGrafanaJenkinsKubernetesLinuxNagiosPerlPrometheusPuppetPythonRubySplunkTerraform
Reposted 21 Days AgoSaved
Remote
United States
200K-300K Annually
Expert/Leader
200K-300K Annually
Expert/Leader
Industrial • Manufacturing
As a Senior ASIC Design Verification Engineer, you will ensure the verification of SoCs, collaborate with cross-functional teams, and contribute to a cohesive work environment.
Top Skills: C/C++PythonSystem VerilogTclUvmVerilog
Reposted 21 Days AgoSaved
In-Office
San Jose, CA, USA
200K-300K Annually
Senior level
200K-300K Annually
Senior level
Industrial • Manufacturing
Responsible for all aspects of digital SoC verification, collaborating with architects, designers, and SW engineers on automotive communication semiconductors.
Top Skills: C/C++PythonSystem VerilogTclUvmVerilog
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Reposted 21 Days AgoSaved
In-Office
Waltham, MA, USA
89K-170K Annually
Senior level
89K-170K Annually
Senior level
Healthtech
Lead design assurance for the Opal system, ensuring quality and regulatory compliance in medical devices. Mentor junior engineers and manage complex projects.
Top Skills: CadFmeaIec 62304Iso 13485Software Testing FrameworksStatic Code Analysis Tools
Reposted 21 Days AgoSaved
Hybrid
3 Locations
Senior level
Senior level
Hardware • Software
Responsible for end-to-end functional verification of mixed-signal ASICs, developing verification plans, testbenches, coverage analysis, and collaborating with cross-functional teams.
Top Skills: HvlSystemverilogUvmVerilogVhdl
Reposted 21 Days AgoSaved
Hybrid
3 Locations
5-1000M Annually
Senior level
5-1000M Annually
Senior level
Hardware • Software
The Design Verification Engineer will conduct end-to-end functional verification of custom mixed-signal ASICs, develop testbenches, and collaborate across teams to enhance verification processes.
Top Skills: AvmOvmSystemverilogUvmVeraVerilogVhdl
Reposted 21 Days AgoSaved
Hybrid
3 Locations
Senior level
Senior level
Hardware • Software
The role involves functional verification of ASIC designs, including developing verification plans, testbenches, and collaborating with cross-functional teams to ensure high-quality outcomes.
Top Skills: Mixed-Signal IcsSystemverilogUvmVerilogVhdl
Reposted 21 Days AgoSaved
Hybrid
3 Locations
Junior
Junior
Hardware • Software
The Design Verification Engineer will develop verification plans, perform ASIC functional verification, design UVM testbenches, and collaborate with cross-functional teams to improve verification processes.
Top Skills: AvmOvmSystemverilogUvmVeraVerilogVhdl
Reposted 22 Days AgoSaved
In-Office
Ann Arbor, MI, USA
Senior level
Senior level
Biotech
In this role, you will design and optimize optical systems for the Incucyte product platform, integrating various subsystems and performing system-level testing and verification.
Top Skills: Biomedical EngineeringComsolElectricalLasersMechanicalOptical DesignRay Tracing ApplicationsZmax
22 Days AgoSaved
In-Office or Remote
9 Locations
213K-299K Annually
Senior level
213K-299K Annually
Senior level
Aerospace
Lead mixed-mode design verification methodology for complex SoCs. Define co-simulation EDA environment, create Verilog/SystemVerilog testbenches and behavioral models, support analog/digital teams, and perform AMS simulations for block- and chip-level verification.
Top Skills: AmsCadence VirtuosoCmosEdaFinfetMatlabPythonSystemverilogVerilog
22 Days AgoSaved
In-Office
Westborough, MA, USA
151K-223K Annually
Senior level
151K-223K Annually
Senior level
Artificial Intelligence • Automotive • Semiconductor
SoC-level design verification engineer responsible for developing and maintaining UVM testbenches and verification environments, creating test plans and strategies, writing tests to meet coverage goals, debugging failures, and collaborating with designers to resolve issues.
Top Skills: ArmCC++CxlEthernetLinuxPciePerlPythonSocSystemverilogUvmVerilog
22 Days AgoSaved
In-Office
Tampa, FL, USA
Expert/Leader
Expert/Leader
Professional Services • Transportation • Consulting • Industrial
Lead Florida drainage discipline, manage/design stormwater and hydraulic systems, oversee permitting and quality control, mentor staff, coordinate with roadway designers, and drive business development for FDOT and municipal clients.
Top Skills: Autocad Civil 3DGisHec-RasHy-8ExcelMicrostationOpenroadsOrd-SudaSmsSrh-2DStormwise (Icpr)
22 Days AgoSaved
In-Office
Orland, CA, USA
81K-150K Annually
Senior level
81K-150K Annually
Senior level
Other
Lead mechanical engineer responsible for MEP design from concept through construction, overseeing HVAC systems (chilled/hot/condenser water, steam, fuel oil, ductwork, controls), managing scope, budgets, and schedules, mentoring staff, performing and reviewing calculations and design documents, ensuring code compliance, coordinating multidisciplinary teams, and serving as primary client contact.
Top Skills: Arc Flash Analysis SoftwareBluebeamEnergy Modeling SoftwareHvac Load Calculation SoftwareMS OfficeRevit
22 Days AgoSaved
In-Office
Orlando, FL, USA
66K-85K Annually
Junior
66K-85K Annually
Junior
Other
Support design and delivery of mechanical (MEP) systems—primarily HVAC—by preparing drawings, calculations, specifications, and construction documents; coordinate with multidisciplinary teams, perform site visits, assist with submittals/RFIs, and support projects through design and construction phases.
Top Skills: AutocadBluebeamEnergy ModelingHvac Load Calculation ToolsMS OfficeRevit
22 Days AgoSaved
In-Office
3 Locations
191K-269K Annually
Expert/Leader
191K-269K Annually
Expert/Leader
Artificial Intelligence • Cloud • Information Technology • Software
Lead cross-functional teams to define and enhance Design for Manufacturability (DFM) and DTCO methodologies for advanced logic technologies. Analyze silicon yield, refine yield tools/flows, develop rules to avoid layout marginalities, support inline yield detection and optimization, and drive scribe line and test-chip design improvements to accelerate high-volume manufacturing ramps.
Top Skills: Backside Power DeliveryCadCoding/ScriptingDevice PhysicsDfmDrcDtcoDtpFinfetGaa FetOpcPhysical DesignProcess IntegrationRetScribe Line LayoutSramStandard CellsTest Chip DesignWaiver ManagementYield Analysis
22 Days AgoSaved
In-Office
4 Locations
101K-194K Annually
Mid level
101K-194K Annually
Mid level
Artificial Intelligence • Cloud • Information Technology • Software
Support installation, maintenance, and automation of design and compute environments for Intel PDKs and EDA tools. Troubleshoot designer issues to TapeOut, integrate new tools and workflows, collaborate with PDK, flow, product, and compute teams, provide training/documentation, and interact with EDA vendors to ensure required features and quality.
Top Skills: Back-End Eda ToolsBashEda ToolsFront-End Eda ToolsIntel PdkIonLinuxNetbatchPdk Flows (Cheetah)PerlPythonTclTcshVerilogVhdl
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