Top Design Engineer Jobs

Lead highway design efforts on complex infrastructure projects, providing senior-level engineering, coordination, scope and budget management, mentoring, technical oversight, and cross-discipline collaboration to ensure on-time, high-quality delivery.

Develop and maintain advanced verification environments using SystemVerilog/UVM/OVM; design UVM agents and behavioral models; implement assertions and coverage; create random and directed tests; debug simulation failures and analyze coverage; collaborate with design teams on SoC/IP verification.

Develop and maintain verification environments using SystemVerilog and UVM/OVM; create UVM agents, behavioral models, assertions, coverage; write random and directed tests; analyze/debug simulation failures and coverage; collaborate with design teams to resolve complex verification issues.

Design and verify FPGA-based modem and physical-layer implementations for space communications. Architect RTL for SoC FPGAs, implement DSP/modem functions, develop UVM/self-checking verification, perform timing closure and hardware bring-up, and support radiation-tolerant, high-reliability aerospace designs.

Lead architecture, RTL development, and design automation for a configurable IO subsystem for microcontroller/SoC platforms. Define specs, implement parameterized and Python generator-based flows, develop SystemVerilog RTL and UVM testbenches, support synthesis/STA/timing closure, collaborate cross-functionally, and apply AI/ML to improve productivity and verification.

The role involves sustaining engineering for automation hardware, including component selection, electrical design updates, testing, troubleshooting, and cross-functional collaboration.

As a Mechanical Engineer II, you will design and analyze mechanical subassemblies, conduct feasibility studies, execute design changes, and collaborate with cross-functional teams to ensure product quality and reliability.

Drive verification from architecture/design to production silicon by developing scalable methodology, creating testbenches and portable tests, executing subsystem and full-chip verification, achieving coverage closure, and leading reviews toward sign-off, tapeout, and silicon bring-up.

Create and maintain 3D CAD models and engineering drawings compliant with ASME; check drawings for accuracy; identify and recommend design revisions; maintain configuration baseline and support PLM systems; support production lifecycle management; collaborate with multi-disciplinary teams; travel up to 25%; must hold an active U.S. Secret clearance.

Serve as a technical evangelist for Cadence analog design tools and agentic workflows. Demonstrate product capabilities to customers, resolve customer issues with application engineers, advocate customer needs to R&D, and help define improved use models and user interfaces to advance analog/RF/mixed-signal circuit design workflows.

The role involves leading the design of custom silicon, shaping micro-architecture, collaborating on verification, and managing cross-team interactions, while building a new team.

This role involves verifying SoCs, developing verification environments, writing test plans, and debugging issues, primarily using System Verilog and UVM.

Lead verification strategy and execution for complex digital and mixed-signal designs. Architect UVM/SystemVerilog environments, develop advanced test benches, define coverage metrics, lead debug and post-silicon validation, mentor junior engineers, and drive methodology improvements while collaborating with design teams and customers.

The Senior Principal Engineer will define and develop system architectures for high-speed industrial products, collaborating closely with customers and stakeholders. Responsibilities include product definition, development, and support, along with participation in business development and technical troubleshooting.

Lead design and development of composite phenolic and elastomer mechanical components from concept through production. Perform CAD modeling, FEA and hand calculations, prototyping, testing, and root-cause analysis. Define scalable manufacturing and assembly processes, create process control documentation, and collaborate with Manufacturing and Quality to improve production and ensure aerospace/defense compliance and production readiness.

Coordinate software release activities across multiple controllers and suppliers, serve as liaison between hardware DREs, function owners and calibration teams, lead HW/SW interface troubleshooting, ensure hardware support for software milestones, identify and escalate risks to leadership.

Provide process engineering and design support for refinery capital and expense projects, troubleshooting, commissioning, and turnarounds. Prepare design packages, perform calculations, evaluate solutions, manage external studies, support safety and hazard analyses, lead multi-functional teams, and mentor junior engineers to ensure safe, compliant, and cost-effective process designs.

Lead digital ASIC verification at block and system level: write and execute test plans, develop test harnesses and regressions, close coverage, support pre-silicon verification, chip bring-up and post-silicon validation, and collaborate with cross-disciplinary teams to verify complex digital designs.

Lead digital ASIC verification at block and system levels: author and execute test plans, develop test harnesses and regressions, drive coverage closure, support pre-silicon verification, chip bring-up and post-silicon validation, and collaborate with cross-disciplinary teams to verify complex designs.

Verify digital ASICs at block and system level: write and execute test plans, build SystemVerilog (UVM and non-UVM) testbenches, run regressions and close coverage, automate tests with Python/MATLAB, and support pre-silicon verification, chip bring-up and post-silicon validation.

Lead digital ASIC verification at block and system levels: write and review test plans, develop test harnesses and sequences, run regressions and close code/functional coverage, and support pre-silicon verification, chip bring-up, and post-silicon validation for complex digital designs.

Develop and execute digital ASIC verification at block and system levels. Build SystemVerilog/UVM and non-UVM testbenches, write test plans, run regressions, close coverage, automate test generation with Python and MATLAB, and support pre-silicon verification, chip bring-up, and post-silicon validation.

Develop and execute digital ASIC verification at block and system levels. Create SystemVerilog/UVM and non-UVM testbenches, write test plans, run regressions, close coverage, automate test generation with Python and MATLAB, and support pre-silicon, chip bring-up and post-silicon validation.

Lead digital ASIC verification at block and system levels: write and execute test plans, develop testbenches and harnesses, run regressions, close coverage, and support pre-silicon verification, chip bring-up, and post-silicon validation for space-qualified ASICs.

Develop and execute digital ASIC verification at block and system level. Build SystemVerilog (UVM and non-UVM) testbenches, write test plans, run regressions, close coverage, automate test generation with Python and MATLAB, and support pre-silicon verification through post-silicon validation and chip bring-up.