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24 Days AgoSaved
In-Office
San Jose, CA, USA
144K-267K Annually
Senior level
144K-267K Annually
Senior level
Cloud • Hardware • Software • Semiconductor
The role involves providing technical support for Cadence's verification tools, developing customer-specific verification requirements, and creating technical presentations. The engineer collaborates with customers, R&D, and sales teams to provide innovative solutions and ensure customer success.
Top Skills: AmbaCC++DdrJtagPciePerlPythonSystemcSystemverilogTclUartUvmVerilogVhdl
24 Days AgoSaved
In-Office
San Jose, CA, USA
179K-259K Annually
Expert/Leader
179K-259K Annually
Expert/Leader
Artificial Intelligence • Internet of Things • Machine Learning • Semiconductor
Design and develop EDA tools and flows focusing on ML/AI integration for chip design efficiency. Collaborate across teams to enhance design automation processes.
Top Skills: CadencePythonPyTorchScikit-LearnSiemens/Mentor Eda ToolsSynopsysTclTensorFlow
Reposted 24 Days AgoSaved
Easy Apply
In-Office
Casa Grande, AZ, USA
Easy Apply
100K-110K Annually
Mid level
100K-110K Annually
Mid level
Aerospace • Information Technology • Software • Biotech • Design
As a Design and Release Engineer for Airbags, you will research, design, develop, and test airbag systems for vehicles. Responsibilities include analyzing proposals, collaborating with drafters, and maintaining product development history.
Top Skills: Computer Aided Design (Cad)
Reposted 24 Days AgoSaved
In-Office
San Jose, CA, USA
158K-293K Annually
Senior level
158K-293K Annually
Senior level
Cloud • Hardware • Software • Semiconductor
The Application Engineering Architect collaborates with customers in Advanced Packaging, performs technical demonstrations, and develops solutions based on customer needs.
Top Skills: 2.5D-Ic Packaging TechnologiesCadCadence Ic Packaging Tools
25 Days AgoSaved
In-Office
3 Locations
120K-192K Annually
Senior level
120K-192K Annually
Senior level
Semiconductor
The Design Implementation Engineer will work on place and route, timing closure, and floor-planning. Responsibilities include using design verification tools, optimizing power, and ensuring silicon accuracy.
Top Skills: CaliberIcc2InnovusLecPrimetime
25 Days AgoSaved
In-Office
Fort Collins, CO, USA
108K-173K Annually
Senior level
108K-173K Annually
Senior level
Semiconductor
The Design Automation DFT Engineer will develop and support design automation software tools for ASIC development while collaborating with IC designers and EDA vendors to resolve issues.
Top Skills: BashC++PerlPythonRubyTcl
25 Days AgoSaved
In-Office
San Jose, CA, USA
141K-226K Annually
Senior level
141K-226K Annually
Senior level
Semiconductor
Responsible for advanced verification tasks in SoC and IP development, including environment development, test case creation, coverage analysis, and design debugging.
Top Skills: C/C++Object-Oriented Verification LanguagesPerlRtl Verification MethodologiesSystem VerilogUvm
25 Days AgoSaved
In-Office
San Jose, CA, USA
141K-226K Annually
Senior level
141K-226K Annually
Senior level
Semiconductor
The Design Verification Engineer will develop verification environments using System Verilog and UVM, create verification components, analyze simulation failures, and produce test cases.
Top Skills: C/C++OvmPerlRtlSystem VerilogUvm
25 Days AgoSaved
In-Office
San Jose, CA, USA
120K-192K Annually
Senior level
120K-192K Annually
Senior level
Semiconductor
Design interposer layouts for high-speed interfaces while collaborating with cross-functional teams. Requires scripting for automation and expertise in 2.5D/3D designs.
Top Skills: Cadence InnovusCadence IntegrityMentor Graphics CalibrePythonSkillSynopsys 3Dic CompilerTcl
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Reposted 25 Days AgoSaved
In-Office
San Jose, CA, USA
150K-275K Annually
Senior level
150K-275K Annually
Senior level
Artificial Intelligence • Hardware • Software
Ensure first silicon delivery for ASICs, develop test benches, and possess experience in hardware verification and scripting languages.
Top Skills: Hbm3PythonSystem VerilogVerilator
Reposted 25 Days AgoSaved
In-Office
Santa Clara, CA, USA
161K-260K Annually
Senior level
161K-260K Annually
Senior level
Artificial Intelligence • Machine Learning • Software
The Design Verification Engineer will lead SoC verification cycles, utilizing methodologies like UVM/OVM, and contributing to innovative AI architectures.
Top Skills: CC++OvmSystemcSystemverilogUvm
Reposted 25 Days AgoSaved
In-Office
Pittsburgh, PA, USA
Mid level
Mid level
Consulting
The Civil Engineer will design transportation projects, develop construction specifications, manage utility conflicts, and collaborate on project deliverables in a hybrid work environment.
Top Skills: Autocad Civil 3DBentley Openroads DesignerMS Office
Reposted 25 Days AgoSaved
Easy Apply
In-Office
San Jose, CA, USA
Easy Apply
157K-243K Annually
Senior level
157K-243K Annually
Senior level
Semiconductor
Develop verification infrastructure for AI accelerator IP blocks, create test plans, debug, and mentor junior engineers in a collaborative environment.
Top Skills: C/C++PerlPythonSystem VerilogUvm
Reposted 25 Days AgoSaved
Easy Apply
In-Office
2 Locations
Easy Apply
100K-500K Annually
Senior level
100K-500K Annually
Senior level
Hardware • Manufacturing
The Design for Test Engineer will implement DFT features in RTL, analyze test coverage, and support silicon bring-up for advanced AI/ML architectures.
Top Skills: AtpgJtagSynopsys VcsSystemverilogUvmVerdiVerilog
Reposted 25 Days AgoSaved
Easy Apply
In-Office
3 Locations
Easy Apply
100K-500K Annually
Mid level
100K-500K Annually
Mid level
Hardware • Manufacturing
The engineer will focus on pre-silicon verification of DFD logic in AI SoCs, developing environments, analyzing coverage gaps, and automating testing flows.
Top Skills: Ai Productivity ToolsIjtagSiemens TessentUvm
4 Months AgoSaved
Easy Apply
Hybrid
Los Angeles, CA, USA
Easy Apply
200K-250K Annually
Senior level
200K-250K Annually
Senior level
Events • Mobile
As a Senior Frontend Engineer, you will design, develop, and maintain user experiences across platforms, focusing on design systems and mentoring team members.
Top Skills: FigmaReactReact NativeStorybookTypescript
4 Months AgoSaved
Easy Apply
Hybrid
Aliso Viejo, CA, USA
Easy Apply
200K-250K Annually
Senior level
200K-250K Annually
Senior level
Events • Mobile
As a Senior Frontend Engineer, you'll design and develop user experience systems, mentor team members, and ensure code quality.
Top Skills: Ci/CdFigmaReactReact NativeStorybookTypescript
4 Months AgoSaved
Easy Apply
Hybrid
New York, NY, USA
Easy Apply
200K-250K Annually
Senior level
200K-250K Annually
Senior level
Events • Mobile
As a Senior Frontend Engineer, you will design, develop, and maintain design systems and reusable components while mentoring team members and collaborating with designers and engineers.
Top Skills: FigmaReactReact NativeStorybookTypescript
7 Months AgoSaved
In-Office
Arlington, VA, USA
107K-140K Annually
Mid level
107K-140K Annually
Mid level
Edtech
The ASIC/FPGA Research Engineer will engage in digital hardware design, work with advanced prototypes, and support research efforts within a collaborative team setting.
Top Skills: C++GoLinuxPythonVerilogVhdl
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