Top Design Engineer Jobs

The FPGA Circuit Design Engineer is responsible for designing, developing, and optimizing FPGA circuits, conducting simulations, and working on microarchitecture and SoC integration.

Responsible for enhancing existing products, creating designs using 3D CAD software, generating design documentation, and assisting in product development and testing processes.

The intern will design, prototype, and ship computing interfaces for brain-computer interaction, collaborating with experts in various fields.

The Sr. Design Engineer will perform technical tasks, suggest product improvements, coordinate projects, and provide guidance to junior staff.

The role involves architecting and engineering global network infrastructures, focusing on WAN optimization, routing protocols, and network automation, while leading projects and documenting solutions.

The Sr. Design Engineer will develop systems using Java with multi-threading, engage in customer interaction to gather requirements, and contribute to design discussions.

The Design Engineer is responsible for applying engineering theories and practices, collaborating on development projects, creating 3D models and detailed design documentation, and ensuring product quality and specifications are met.

The candidate will assure product quality through test automation, code inspections, peer reviews, and white-box testing using Microsoft technologies.

Lead new product development projects, manage design processes, create specifications, perform simulations, and mentor other engineers to ensure successful product design and implementation.

Lead the design and integration of electrical systems for wearable devices, guiding junior engineers and collaborating with multidisciplinary teams to drive innovation.

The Principal Analog Design Engineer will design high-speed analog circuits and collaborate with teams to optimize performance in photonic AI systems.

The Design Engineer will work on RF chain for auto-band systems, focusing on PCB design and building system parts.

The Mechanical Design Engineer will lead the design process, manage documentation and drawings, and liaise with vendors for prototype testing and part replacement.

The Network Design Engineer is responsible for planning, designing, and maintaining lab network components while providing technical support for network communications.

Develop microarchitecture design and RTL for ML/AI accelerator ASICs while collaborating with various engineering teams to ensure high performance and low power designs.

Develop microarchitecture design and RTL for ML/AI accelerator ASICs, collaborate with teams, and manage RTL implementation for high-performance designs.

Lead the design, planning, and optimization of wireless networks for a LEO satellite constellation. Collaborate with teams to ensure high-performance end-to-end solutions and contribute to technical leadership and best practices.

The Senior Antenna Design Engineer will lead the design, simulation, and validation of advanced antenna systems for LEO satellites, using HFSS. Responsibilities include optimizing phased array antennas, collaborating with cross-functional teams, and providing mentorship to junior staff.

As a Senior ASIC Front-End Design Engineer, you will oversee digital SoC design, collaborating to create automotive communication semiconductors, ensuring target performance and area goals are met.

As a Senior ASIC Front-End Design Engineer, you'll manage digital SoC design, collaborating on high-performance custom silicon for automotive communication systems.

Design high-performance analog-to-digital and digital-to-analog converters, evaluate silicon, and oversee layout in advanced CMOS processes.

Design and verify high-performance digital and mixed-signal ICs, focusing on RTL design, behavioral modeling, and digital control circuits.

Design and automate high-performance analog and mixed-signal ICs, lead a team, and innovate methodologies for parameterizing designs.

The role involves synthesizing, placing, and routing high-speed designs, collaborating with RTL teams, and optimizing designs for power/performance area.

Lead the design and development of high-performance RTL solutions for the Cerebras Wafer Scale Engine, collaborating with teams and managing ASIC vendors.