Top Design Engineer Jobs

Join NVIDIA's Standard Cell Library team to develop and optimize standard cell templates, define DFM methodologies, improve library validation and release flow, script automation (Perl/Python/Tcl/C++/SKILL), and collaborate with CAD vendors and cross-functional teams.

Design and implement algorithms and tools for chip-level placement, reshaping, and global routing. Develop computational geometry, placement, routing and graph-optimization solutions, apply machine learning for design space exploration, extend GUIs for debugging/visualization, and collaborate with design teams to deploy high-performance C++ tools impacting next-generation AI chip physical layouts.

Develop physical design methodologies for graphics processors and SOCs, focusing on innovative solutions to PPA problems and ML-based development.

Lead design control and risk management activities for new and sustaining medical device products. Support verification/validation, usability studies, process qualifications, audits, and QMS updates while training staff and ensuring compliance with regulatory standards.

The engineer will implement RTL to GDSII design, including synthesis, placement, routing, and physical signoff verification, leveraging EDA tools.

The Senior DFD Architect will architect silicon debug capabilities for NVIDIA's GPUs, drive efficiency improvements, mentor junior engineers, and collaborate with cross-functional teams to enhance debug features.

Lead design assurance activities across product development and sustaining projects, managing design controls, risk management (ISO 14971), verification/validation, process qualifications, audits, and QMS documentation to ensure regulatory compliance and product safety.

As a Physical Design Principal Engineer, you'll lead SOC implementation and verification, ensuring design and timing closure from RTL to GDS, collaborating with teams on architectural studies.

Lead verification planning and develop UVM-based testbenches for mixed-signal ASICs. Implement functional verification, directed/constraint-random tests, gate-simulations, coverage and failure analysis, digital/mixed-signal modeling, and regression/debug infrastructure.

Lead verification planning and testbench development using UVM/HVLs for mixed-signal ASICs. Implement functional verification, directed/constraint-random tests, gate-simulations, coverage analysis, failure analysis, and regression/debug infrastructure improvements.

Perform block- and chip-level functional verification of mixed-signal ASICs, develop verification plans and constrained-random testbenches (UVM/OVM), implement coverage and scoreboards, run gate-level simulations and HW-accelerated/emulated tests, triage regressions, and collaborate with digital/analog designers and test teams for pre- and post-silicon validation.

Perform block- and chip-level functional verification of mixed-signal ASICs: develop verification plans, testbenches, constraint-random and directed tests, coverage closure, regression triage, gate-level simulation analysis, and collaborate with designers and test teams for pre- and post-silicon validation.

Lead and execute block- and chip-level functional verification for mixed-signal ASICs. Develop verification plans, testbenches, constraint-random and directed tests, coverage closure, regression triage, gate-level simulation analysis, and collaborate with cross-functional teams for pre- and post-silicon validation.

Participate in mixed-signal ASIC verification: plan verification, develop UVM testbenches, implement functional verification, create constrained-random tests, perform failure and coverage analysis, support gate-simulations, regression debug, and verification infrastructure improvements.

Lead functional verification for mixed-signal ASICs including verification planning, UVM testbench development, constraint-random and directed tests, coverage and failure analysis, digital/mixed-signal modeling, gate simulations, and regression/debug infrastructure.

Lead design-system integration for next-generation engineering tools: define architecture, develop software, provide technical leadership, drive reuse and efficiency, support legacy modernization, and collaborate with product line leaders across turbomachinery teams.

Lead design control and risk management for new and sustaining medical device projects. Maintain risk files per ISO 14971, support verification/validation, usability studies, process qualifications, audits, and QMS procedure updates. Provide technical support for regulatory audits and train staff on quality and QMS principles.

As a CPU Physical Design Automation Engineer, you will develop and support tools for backend physical design and analyze designs for performance and reliability.

The Senior Design Reliability Engineer will lead technical reviews, oversee flight systems testing, ensure design compliance, and foster cross-functional collaboration to enhance engineering reliability in space station development.

The Principal Process Engineer leads the development of hygienic process systems, resolves manufacturing challenges, and provides technical leadership across multiple teams while adhering to regulatory standards.

Lead architecture and design of high-speed SerDes ICs for automotive applications, developing new technologies and specifications, while collaborating cross-functionally.

Responsible for traffic operations project plans, designs, and studies including signal designs, cost estimates, and project reporting. Works collaboratively on the development and execution of engineering solutions.

The role involves supporting MOSIS 2.0 customers in analog and digital circuit design and layout, engaging in academic research, and collaborating on projects. Responsibilities include technical guidance, teaching classes, and preparing design documentation.

Develop and analyze mechanical systems, oversee fabrication and testing, guide less experienced engineers, and improve processes.

Design and build features that enhance user capabilities with AI, focusing on innovative interaction and integrating research insights into products.