Top Design Engineer Jobs

Designs and develops silicon photonics integrated circuits, managing the entire development process, including testing and analysis for cutting-edge photonic devices and systems-on-chip.

Develop and apply AI techniques to enhance pre-silicon verification methodologies, collaborate with machine learning engineers, and improve design lifecycles.

The Formal Verification Engineer will develop innovative AI-driven solutions for chip design, employing formal methods and collaborating with ML and software teams.

The Staff Design Release Engineer will own the design and integration of compute and connectivity subsystems in autonomous vehicles, overseeing technical execution, documentation, and supplier alignment throughout the product lifecycle.

The Principal Design Verification Engineer will lead verification strategies, execute high-performance CPU subsystem verification, and improve methodologies, with a focus on CPU core and coherent interconnect verification.

The Principal Design Verification Engineer will lead ASIC and FPGA verification processes, develop and execute test plans, and ensure design integrity through extensive validation processes. They will work with cross-disciplinary teams and contribute to innovative designs for space technology, particularly for Starlink.

The Principal Design Verification Engineer will verify ASICs/FPGA designs, lead test plans, and ensure designs meet specifications. Collaborating with cross-disciplinary teams, the role involves pre-silicon verification and post-silicon validation.

The Principal Design Verification Engineer will lead ASIC and FPGA verification, develop test plans, and validate designs for Starlink's infrastructure. Significant experience in design verification is required.

The Sr. Mechanical Engineer will design and develop machinery for the Starship production, collaborating with a team to maximize production efficiency.

As a Mechanical Engineer in Machine Design for Starship at SpaceX, you will design custom machinery and infrastructure, collaborate on vehicle design, perform structural analysis, and create engineering models. Responsibilities include supporting machine activation and manufacturing planning while working in a dynamic team environment.

The principal design verification engineer will lead ASIC verification efforts, ensuring designs meet specifications and are validated through hands-on execution and development of test plans.

The Technical Staff Engineer will design and develop analog ICs for Ethernet and USB products, collaborate with cross-functional teams, and ensure high-quality standards. Responsibilities include creating specifications, performing simulations, and meeting aggressive timelines for product development.

Responsible for verification of networking ASICs, including developing test plans, environments, and executing verification processes using SystemVerilog. Requires strong experience in digital design and verification techniques.

Design electrical control panels, MCCs, and VFD panels for low-voltage industrial systems. Create PLC I/O schematics, panel layouts, BOMs, motor three-line diagrams, cable schedules, and construction scopes. Coordinate with clients, OEMs, contractors, support field start-ups and bid walks, estimate project effort, and travel to client sites (~10%).

Design and support fluid and mechanical systems for rocket engine ground test facilities across the full lifecycle. Produce P&IDs, models, drawings, and analyses; apply fluid mechanics and structural fundamentals to cryogenic, propellant, and high-pressure gas systems; support supplier coordination, hazard assessments (PHA/HAZOP), fabrication/start-up, configuration management in Windchill, and on-site commissioning and field operations.

Design and analyze production, test, integration, and advanced manufacturing tooling and custom machines for aerospace programs. Lead tooling projects from concept through fabrication, installation, proof testing, and commissioning while collaborating with designers and manufacturing to meet safety, cost, quality, and schedule goals.

Lead verification planning and execution for complex ASIC/SoC digital subsystems. Develop UVM testbenches, reference models, scoreboards, protocol monitors, and assertions. Drive coverage closure, regression health, and verification signoff. Identify corner cases, collaborate across design, systems, DFT, firmware, and physical design, and support emulation, prototyping, and post-silicon debug.

Develop analog and system models to verify mixed-signal SoC functionality and connectivity. Build mixed-signal simulation testbenches, collaborate with design and architecture teams, run pre-silicon verification, and work with designers to debug and resolve issues.

Develop, deploy, and own RTL-to-GDSII physical design methodology and CAD flows for IP delivery. Automate PPA exploration, document flows, partner with design teams and EDA vendors, qualify new nodes/PDKs and EDA releases, and apply ML/LLMs where they improve flow optimization and scalability.

Ensure Falcon and Dragon flight hardware meets design criteria and reliability standards. Perform design reviews and test approvals, develop requirements and verification approaches, enable aircraft-like operations, drive design improvements with hardware teams, and build specialized design/analysis tools.

Develop and execute verification plans and environments for complex digital and mixed-signal IP. Create UVM testbenches, random and directed tests, assertions, functional models; perform coverage closure, debug RTL and gate-level failures, and collaborate with design teams and EDA vendors. May work with emulation and FPGA prototyping and adopt advanced verification flows.

Lead development and execution of test plans and CONOPs for RF and cloud-enabled systems. Oversee instrumentation setup, demonstrations, field exercises, data collection and analysis, system deployment/configuration, and RF system testing across on-prem and cloud environments. Support BAST RAD portfolio with up to 25% travel and collaboration between Melbourne, FL and Space Park, CA.

Lead and execute design transfers from development through manufacturing and post-launch. Define system-level I&T requirements, develop test plans, identify and mitigate I&T and manufacturing risks, document best practices, and coordinate cross-functional multi-site teams. Support program planning, schedule/cost control, and customer/government interactions; travel occasionally.

Lead design and implementation of secure embedded controller and cryptographic ICs. Drive architecture, RTL development, verification, and bring-up. Support integration activities (lint, CDC, synthesis, DFT), work with physical design on STA/power/floorplanning, debug hardware/firmware interactions, and collaborate across global teams to deliver automotive, industrial, and security-focused ASIC/FPGA products.

Lead IO and pad ring planning for advanced SoC storage and memory controller designs. Create and validate pad ring DEFs, bump maps, IO netlists, and handoff deliverables. Coordinate with architecture, IP, packaging, implementation, foundry, and verification teams to ensure IO/package compliance, support silicon debug, and drive design improvements.